From patchwork Tue Jun 21 10:44:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12889018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4893CCA473 for ; Tue, 21 Jun 2022 10:47:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A74210FE14; Tue, 21 Jun 2022 10:47:01 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id AE74A10FCEC; Tue, 21 Jun 2022 10:46:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655808415; x=1687344415; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eM5Dcjm/HcptWxgw8J7RQEwYZvdlz8zP4bPNsCNYTEY=; b=Mlup0aXj/neDIiMwUcYu6d7oIw+J7t2DkorxV1SeG2SAa6ZN2obFFKwJ vsk9oCdBRMlJlCZCQUEfTD/gOoLMfRmlKHvOpN02OCtZC9tSvBgwq0qUB X4KqbmsjKX/X+BTewpHxwj1GHQR5eGWuCI0mAPjyyZ/wtZetvkfEy8dxZ pjo7WjXQnfzglnj5Fte/uuuxr3WcjdwCXRp+VYBfC61olYGoCqFpMq9Ga W/Yd8ndc7wI8k5+aMuS2hKFxVBNPjz2UPTNEdAb8q1n+iTipaeKVehdrO 9gU3zfoeuW63HP42d8p+rR6vC9qxWUHLrnQqJFv34fySgWbxrPRaaXLZY w==; X-IronPort-AV: E=McAfee;i="6400,9594,10384"; a="263121961" X-IronPort-AV: E=Sophos;i="5.92,209,1650956400"; d="scan'208";a="263121961" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2022 03:46:55 -0700 X-IronPort-AV: E=Sophos;i="5.92,209,1650956400"; d="scan'208";a="562327134" Received: from jasonmor-mobl1.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.213.200.10]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jun 2022 03:46:52 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Jun 2022 11:44:31 +0100 Message-Id: <20220621104434.190962-10-matthew.auld@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220621104434.190962-1-matthew.auld@intel.com> References: <20220621104434.190962-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 09/12] drm/i915/selftests: ensure we reserve a fence slot X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Daniel Vetter , Kenneth Graunke , dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" We should always be explicit and allocate a fence slot before adding a new fence. Signed-off-by: Matthew Auld Cc: Thomas Hellström Cc: Lionel Landwerlin Cc: Tvrtko Ursulin Cc: Jon Bloomfield Cc: Daniel Vetter Cc: Jordan Justen Cc: Kenneth Graunke Cc: Akeem G Abodunrin Reviewed-by: Thomas Hellström --- drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c index 5bc93a1ce3e3..7c95b6768610 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c @@ -1221,8 +1221,10 @@ static int __igt_mmap_migrate(struct intel_memory_region **placements, expand32(POISON_INUSE), &rq); i915_gem_object_unpin_pages(obj); if (rq) { - dma_resv_add_fence(obj->base.resv, &rq->fence, - DMA_RESV_USAGE_KERNEL); + err = dma_resv_reserve_fences(obj->base.resv, 1); + if (!err) + dma_resv_add_fence(obj->base.resv, &rq->fence, + DMA_RESV_USAGE_KERNEL); i915_request_put(rq); } i915_gem_object_unlock(obj);