From patchwork Tue Jul 12 22:05:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 12915744 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1A78C43334 for ; Tue, 12 Jul 2022 22:05:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C8A5E96FB5; Tue, 12 Jul 2022 22:05:19 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id C8E8996FB1; Tue, 12 Jul 2022 22:05:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657663518; x=1689199518; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=H+F5/F4+SQV3JoKB52Pr+QhDI+h9InnInbzhTUs/FKU=; b=DA+QGPg3VSjnNarRYDfDrWR2W80+y3z65ZQ7A/DXPIV41wPQPFhStYEq ziv3nmeY7ZWdnPe8QlYeTc/6Fjlg+BjQEqGXnMwEKiLZyYgh7qG+B+eo0 u9HRManROZO96Zb2S82ij6UwMx4UR6yvChj/uT/ioR7POh4SmX4X5Yq2g qd0eM/YkSb5FIrJjv8opGo/oyvJzPvEPPRUb/KM8ZApvl04NgDe7K5aoa 2apCJy3rkxIpuJlJcvJwqCwEInAbm0oGi0gwoyG0g/JhD2lpRtiFqC7K9 XiGM8s4GeuicpiMlWP1B9ljNk2vFdrsfUs6I7YaIU/KDvfIy7rcb6ITUH g==; X-IronPort-AV: E=McAfee;i="6400,9594,10406"; a="283808515" X-IronPort-AV: E=Sophos;i="5.92,266,1650956400"; d="scan'208";a="283808515" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2022 15:05:18 -0700 X-IronPort-AV: E=Sophos;i="5.92,266,1650956400"; d="scan'208";a="772030031" Received: from mdroper-desk1.fm.intel.com ([10.1.27.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jul 2022 15:05:18 -0700 From: Matt Roper To: intel-gfx@lists.freedesktop.org Date: Tue, 12 Jul 2022 15:05:13 -0700 Message-Id: <20220712220513.3451794-1-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915: Correct ss -> steering calculation for pre-Xe_HP platforms X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Accidental use of a "SLICE" macro where a "SUBSLICE" macro was intended causes the group ID for steering to be calculated incorrectly on pre-Xe_HP platforms. Fixes: 9a92732f040a ("drm/i915/gt: Add general DSS steering iterator to intel_gt_mcr") Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_gt_mcr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c index f8c64ab9d3ca..e79405a45312 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_mcr.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_mcr.c @@ -515,7 +515,7 @@ void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, *group = dss / GEN_DSS_PER_GSLICE; *instance = dss % GEN_DSS_PER_GSLICE; } else { - *group = dss / GEN_MAX_HSW_SLICES; + *group = dss / GEN_MAX_SS_PER_HSW_SLICE; *instance = dss % GEN_MAX_SS_PER_HSW_SLICE; return; }