diff mbox series

[18/23] drm/i915/mtl: DBUF handling is same as adlp

Message ID 20220728013420.3750388-19-radhakrishna.sripada@intel.com (mailing list archive)
State New, archived
Headers show
Series Initial Meteorlake Support | expand

Commit Message

Sripada, Radhakrishna July 28, 2022, 1:34 a.m. UTC
Meteorlake uses a similar DBUF programming as ADL-P.
Reuse the call flow for meteorlake.

Bspec: 49255

Cc: Matt Roper <matthew.d.roper@intel.com>
Original Author: Caz Yokoyama
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Matt Roper Aug. 2, 2022, 5:35 p.m. UTC | #1
On Wed, Jul 27, 2022 at 06:34:15PM -0700, Radhakrishna Sripada wrote:
> Meteorlake uses a similar DBUF programming as ADL-P.
> Reuse the call flow for meteorlake.

Although the patch below is correct, the commit message and subject line
here are extremely misleading.  MTL uses _very_ different
handling/programming of DBUF (via the new PM demand mechanism).  The
only thing that's actually the same is the computation of which dbufs
will be enabled (which is all this patch deals with).

> 
> Bspec: 49255
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Original Author: Caz Yokoyama
> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 58a3c72418a7..d73be4bbaaa3 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4934,7 +4934,7 @@ static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool
>  
>  	if (IS_DG2(dev_priv))
>  		return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);
> -	else if (IS_ALDERLAKE_P(dev_priv))
> +	else if (DISPLAY_VER(dev_priv) >= 14 || IS_ALDERLAKE_P(dev_priv))

An alternative would be to just do

        else if (DISPLAY_VER(dev_priv) >= 13)

here since DG2 is already broken out into its own case above.

But either way,

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

with an updated commit message/subject change.

>  		return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);
>  	else if (DISPLAY_VER(dev_priv) == 12)
>  		return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);
> -- 
> 2.25.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 58a3c72418a7..d73be4bbaaa3 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4934,7 +4934,7 @@  static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes, bool
 
 	if (IS_DG2(dev_priv))
 		return dg2_compute_dbuf_slices(pipe, active_pipes, join_mbus);
-	else if (IS_ALDERLAKE_P(dev_priv))
+	else if (DISPLAY_VER(dev_priv) >= 14 || IS_ALDERLAKE_P(dev_priv))
 		return adlp_compute_dbuf_slices(pipe, active_pipes, join_mbus);
 	else if (DISPLAY_VER(dev_priv) == 12)
 		return tgl_compute_dbuf_slices(pipe, active_pipes, join_mbus);