From patchwork Thu Jul 28 16:26:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12931587 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E96CFC04A68 for ; Thu, 28 Jul 2022 16:27:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1474D10F6BB; Thu, 28 Jul 2022 16:27:46 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4842110F6BB for ; Thu, 28 Jul 2022 16:27:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659025664; x=1690561664; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=mRNuhBVGjiO6sbKqm21tJbg9u9GSU5d/R6kKaeTuHNk=; b=QeT4fh9uHdx4S3H1hxfQuAIn7xREX2+7Im44J85JrckxU+2m4S2UMOzu 1d9xDLFNOwKLoS/zHI9LoynyT/qG9IJLEVc6qIi8EpcFSU0KKTemb/1y4 mZPXLbIiEyEZQmm1lwepkGG00uYgvSijpp2W6FvSD8womQeXxofu9Wllp ijx2dkvV52E35xeRzdU/PRtbw7LG6DgllvnEHlJEXRg2EjT95RA7AMpea gvpK4SXhsTrTBwoEeA45SUOmBTnykut3+qTfmTuo4rs4c7QpTu+00FLvQ eudK4jfTcut+Rb+BjJ48rr1ucEAIM6zre6tKyjjaF1aOvv+rIagFseDgi Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10422"; a="289754281" X-IronPort-AV: E=Sophos;i="5.93,198,1654585200"; d="scan'208";a="289754281" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2022 09:27:02 -0700 X-IronPort-AV: E=Sophos;i="5.93,198,1654585200"; d="scan'208";a="551376186" Received: from kseth-mobl20.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.212.134.144]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Jul 2022 09:27:01 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Thu, 28 Jul 2022 09:26:23 -0700 Message-Id: <20220728162623.28901-1-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/dg2: Add support for DC5 state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" With the latest DMC in place, enabling DC5 on DG2. Cc: Imre Deak Signed-off-by: Anusha Srivatsa Reviewed-by: Madhumitha Tolakanahalli Pradeep --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 13aaa3247a5a..3f84af6beff3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -908,7 +908,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv, return 0; if (IS_DG2(dev_priv)) - max_dc = 0; + max_dc = 1; else if (IS_DG1(dev_priv)) max_dc = 3; else if (DISPLAY_VER(dev_priv) >= 12)