| Message ID | 20220728184907.31796-1-harish.chegondi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/dg2: Add Wa_1509727124 | expand |
On Thu, Jul 28, 2022 at 11:49:07AM -0700, Harish Chegondi wrote: > Bspec: 46052 > Cc: Matt Roper <matthew.d.roper@intel.com> > Signed-off-by: Harish Chegondi <harish.chegondi@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 60d6eb5f245b..b3b49f6d6d1c 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -1078,6 +1078,7 @@ > > #define GEN10_SAMPLER_MODE _MMIO(0xe18c) > #define ENABLE_SMALLPL REG_BIT(15) > +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) > #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) > > #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index e8111fce56d0..434d85aec72b 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -2119,6 +2119,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) > wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); > } > > + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || > + IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_FOREVER) || a0..forever covers all steppins and can be simplified to just IS_DG2_G11(). With that changed, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > + IS_DG2_G12(i915)) { > + /* Wa_1509727124:dg2 */ > + wa_masked_en(wal, GEN10_SAMPLER_MODE, > + SC_DISABLE_POWER_OPTIMIZATION_EBB); > + } > + > if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || > IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { > /* Wa_14012419201:dg2 */ > -- > 2.37.1 >
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 60d6eb5f245b..b3b49f6d6d1c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1078,6 +1078,7 @@ #define GEN10_SAMPLER_MODE _MMIO(0xe18c) #define ENABLE_SMALLPL REG_BIT(15) +#define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index e8111fce56d0..434d85aec72b 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2119,6 +2119,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) || + IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_FOREVER) || + IS_DG2_G12(i915)) { + /* Wa_1509727124:dg2 */ + wa_masked_en(wal, GEN10_SAMPLER_MODE, + SC_DISABLE_POWER_OPTIMIZATION_EBB); + } + if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_A0, STEP_B0) || IS_DG2_GRAPHICS_STEP(i915, G11, STEP_A0, STEP_B0)) { /* Wa_14012419201:dg2 */
Bspec: 46052 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Harish Chegondi <harish.chegondi@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 8 ++++++++ 2 files changed, 9 insertions(+)