From patchwork Sat Aug 27 19:43:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 12957081 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C1A3ECAAD5 for ; Sat, 27 Aug 2022 19:45:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3BD9C10ED32; Sat, 27 Aug 2022 19:45:44 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3598910ED31; Sat, 27 Aug 2022 19:45:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1661629533; x=1693165533; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vc4x2DdBiL7x1R+vGJX/p9tEHwv85Nk81El/oWV4R0E=; b=O8SYyfEapzFdyBqmAuJsqDk4BQJKgskx431FBNEA4lKy2xiJQiEX+9P9 endlbXpYRNgK+xU6fic3QC1LvavRPQzp2WCfLO8k7W2Xk4Ihg6eT/XDYM pa4J+rxIReALE27ymNZRotWH/eQCRYgOSJqmHhzQGwBqevHkJ7wYYrK00 rEtKt685OThSHvJG4qXI+83WOC5I9AhYaJ0PHKvexR6eBOVuEptXbHuTh /uK3RZ/oPKPVupldkpjMSEGs5q6yc964Beb3AkqK345SjaqcEh0hEdkg6 QnA9gqJ6hNFqWleveYoD6jTJ0NA/9gpWIIdCMmo8dhvPJBoOLCxgVCxeu Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10452"; a="320800552" X-IronPort-AV: E=Sophos;i="5.93,269,1654585200"; d="scan'208";a="320800552" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2022 12:45:32 -0700 X-IronPort-AV: E=Sophos;i="5.93,269,1654585200"; d="scan'208";a="587696725" Received: from hluxenbu-mobl1.ger.corp.intel.com (HELO intel.com) ([10.249.44.75]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2022 12:45:28 -0700 From: Andi Shyti To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Date: Sat, 27 Aug 2022 21:43:49 +0200 Message-Id: <20220827194403.6495-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220827194403.6495-1-andi.shyti@linux.intel.com> References: <20220827194403.6495-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC PATCH v3 03/17] drm/i915/gem: expose i915_gem_object_max_page_size() in i915_gem_object.h X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ramalingam C , Thomas Hellstrom , Matthew Auld Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Niranjana Vishwanathapura To reuse i915_gem_object_max_page_size() in upcoming implementation, expose it in i915_gem_object.h Signed-off-by: Niranjana Vishwanathapura Signed-off-by: Ramalingam C Signed-off-by: Andi Shyti --- drivers/gpu/drm/i915/gem/i915_gem_create.c | 16 +++++++++++++--- drivers/gpu/drm/i915/gem/i915_gem_object.h | 2 ++ 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 33673fe7ee0ac..b0aebcc52f83c 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -15,8 +15,17 @@ #include "i915_trace.h" #include "i915_user_extensions.h" -static u32 object_max_page_size(struct intel_memory_region **placements, - unsigned int n_placements) +/** + * i915_gem_object_max_page_size() - max of min_page_size of the regions + * @placements: list of regions + * @n_placements: number of the placements + * + * Calculates the max of the min_page_size of a list of placements passed in. + * + * Return: max of the min_page_size + */ +u32 i915_gem_object_max_page_size(struct intel_memory_region **placements, + unsigned int n_placements) { u32 max_page_size = 0; int i; @@ -99,7 +108,8 @@ __i915_gem_object_create_user_ext(struct drm_i915_private *i915, u64 size, i915_gem_flush_free_objects(i915); - size = round_up(size, object_max_page_size(placements, n_placements)); + size = round_up(size, i915_gem_object_max_page_size(placements, + n_placements)); if (size == 0) return ERR_PTR(-EINVAL); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 6f0a3ce355670..650de22248435 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -47,6 +47,8 @@ static inline bool i915_gem_object_size_2big(u64 size) } void i915_gem_init__objects(struct drm_i915_private *i915); +u32 i915_gem_object_max_page_size(struct intel_memory_region **placements, + unsigned int n_placements); void i915_objects_module_exit(void); int i915_objects_module_init(void);