| Message ID | 20220905102355.176622-3-jouni.hogander@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/psr: Disable PSR2 when SDP is sent on prior line | expand |
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Monday, September 5, 2022 1:24 PM > To: intel-gfx@lists.freedesktop.org > Cc: Hogander, Jouni <jouni.hogander@intel.com>; Kahola, Mika > <mika.kahola@intel.com>; Souza, Jose <jose.souza@intel.com> > Subject: [PATCH 2/2] drm/i915/psr: Disable PSR2 when SDP is sent on prior line > > Selective update doesn't work if SU start address is 0 and start/end SDP is > configured to be sent prior to SU start/end lines. PSR2 has to be disabled in this > case for Alder Lake. > > HSDES: 22012279113 > > Cc: Mika Kahola <mika.kahola@intel.com> > Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 6f03bf16d6f4..90d7cdd743be 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -811,7 +811,8 @@ static bool > _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d > if ((hblank_ns - req_ns) > 100) > return true; > > - if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < > DP_EDP_14b) > + /* Not supported <13 / Wa_22012279113:adl-p */ > + if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < > DP_EDP_14b) > return false; > > crtc_state->req_psr2_sdp_prior_scanline = true; > -- > 2.34.1
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 6f03bf16d6f4..90d7cdd743be 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -811,7 +811,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d if ((hblank_ns - req_ns) > 100) return true; - if (DISPLAY_VER(dev_priv) < 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) + /* Not supported <13 / Wa_22012279113:adl-p */ + if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) return false; crtc_state->req_psr2_sdp_prior_scanline = true;
Selective update doesn't work if SU start address is 0 and start/end SDP is configured to be sent prior to SU start/end lines. PSR2 has to be disabled in this case for Alder Lake. HSDES: 22012279113 Cc: Mika Kahola <mika.kahola@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Jouni Högander <jouni.hogander@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)