| Message ID | 20220909001612.728451-13-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: HuC loading for DG2 | expand |
On 9/8/2022 5:16 PM, Daniele Ceraolo Spurio wrote: > Wait on the fence to be signalled to avoid the submissions finding HuC > not yet loaded. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Tony Ye <tony.ye@intel.com> > Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++++++ > drivers/gpu/drm/i915/i915_request.c | 24 ++++++++++++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h > index 915d281c1c72..52db03620c60 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h > @@ -81,6 +81,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc) > return huc->fw.loaded_via_gsc; > } > > +static inline bool intel_huc_wait_required(struct intel_huc *huc) > +{ > + return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) && > + !intel_huc_is_authenticated(huc); > +} > + > void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p); > > #endif > diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c > index 62fad16a55e8..77f45a3cb01f 100644 > --- a/drivers/gpu/drm/i915/i915_request.c > +++ b/drivers/gpu/drm/i915/i915_request.c > @@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to, > return ret; > } > > +static void i915_request_await_huc(struct i915_request *rq) > +{ > + struct intel_huc *huc = &rq->context->engine->gt->uc.huc; > + > + /* don't stall kernel submissions! */ > + if (!rcu_access_pointer(rq->context->gem_context)) > + return; > + > + if (intel_huc_wait_required(huc)) > + i915_sw_fence_await_sw_fence(&rq->submit, > + &huc->delayed_load.fence, > + &rq->submitq); > +} > + > static struct i915_request * > __i915_request_ensure_parallel_ordering(struct i915_request *rq, > struct intel_timeline *timeline) > @@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq) > struct intel_timeline *timeline = i915_request_timeline(rq); > struct i915_request *prev; > > + /* > + * Media workloads may require HuC, so stall them until HuC loading is > + * complete. Note that HuC not being loaded when a user submission > + * arrives can only happen when HuC is loaded via GSC and in that case > + * we still expect the window between us starting to accept submissions > + * and HuC loading completion to be small (a few hundred ms). > + */ > + if (rq->engine->class == VIDEO_DECODE_CLASS) > + i915_request_await_huc(rq); > + Acked-by: Tony Ye <tony.ye@intel.com> Thanks, Tony > /* > * Dependency tracking and request ordering along the timeline > * is special cased so that we can eliminate redundant ordering
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h index 915d281c1c72..52db03620c60 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h @@ -81,6 +81,12 @@ static inline bool intel_huc_is_loaded_by_gsc(const struct intel_huc *huc) return huc->fw.loaded_via_gsc; } +static inline bool intel_huc_wait_required(struct intel_huc *huc) +{ + return intel_huc_is_used(huc) && intel_huc_is_loaded_by_gsc(huc) && + !intel_huc_is_authenticated(huc); +} + void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p); #endif diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 62fad16a55e8..77f45a3cb01f 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1621,6 +1621,20 @@ i915_request_await_object(struct i915_request *to, return ret; } +static void i915_request_await_huc(struct i915_request *rq) +{ + struct intel_huc *huc = &rq->context->engine->gt->uc.huc; + + /* don't stall kernel submissions! */ + if (!rcu_access_pointer(rq->context->gem_context)) + return; + + if (intel_huc_wait_required(huc)) + i915_sw_fence_await_sw_fence(&rq->submit, + &huc->delayed_load.fence, + &rq->submitq); +} + static struct i915_request * __i915_request_ensure_parallel_ordering(struct i915_request *rq, struct intel_timeline *timeline) @@ -1702,6 +1716,16 @@ __i915_request_add_to_timeline(struct i915_request *rq) struct intel_timeline *timeline = i915_request_timeline(rq); struct i915_request *prev; + /* + * Media workloads may require HuC, so stall them until HuC loading is + * complete. Note that HuC not being loaded when a user submission + * arrives can only happen when HuC is loaded via GSC and in that case + * we still expect the window between us starting to accept submissions + * and HuC loading completion to be small (a few hundred ms). + */ + if (rq->engine->class == VIDEO_DECODE_CLASS) + i915_request_await_huc(rq); + /* * Dependency tracking and request ordering along the timeline * is special cased so that we can eliminate redundant ordering