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[5/6] drm/i915/mtl: Modify CAGF functions for MTL

Message ID 20220909025646.3397620-6-badal.nilawar@intel.com (mailing list archive)
State New, archived
Headers show
Series i915: CAGF and RC6 changes for MTL | expand

Commit Message

Nilawar, Badal Sept. 9, 2022, 2:56 a.m. UTC 
Updated the CAGF functions to get actual resolved frequency of
3D and SAMedia

Bspec: 66300

Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++++++
 drivers/gpu/drm/i915/gt/intel_rps.c     | 7 ++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index dac59c3e68db..ab9a5e66ab34 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1515,6 +1515,14 @@ 
 #define   GEN12_CAGF_MASK			REG_GENMASK(19, 11)
 #define   GEN12_VOLTAGE_MASK			REG_GENMASK(10, 0)
 
+/*
+ * MTL: Workpoint reg to get Core C state and act freq of 3D, SAMedia/
+ * 3D - 0x0C60 , SAMedia - 0x380C60
+ * Intel uncore handler redirects transactions for SAMedia to MTL_MEDIA_GSI_BASE
+ */
+#define MTL_MIRROR_TARGET_WP1          _MMIO(0x0C60)
+#define   MTL_CAGF_MASK                REG_GENMASK(8, 0)
+
 #define GEN11_GT_INTR_DW(x)			_MMIO(0x190018 + ((x) * 4))
 #define   GEN11_CSME				(31)
 #define   GEN11_GUNIT				(28)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 341f96f536e8..3e4abc25f139 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2045,7 +2045,10 @@  u32 intel_rps_read_rpstat(struct intel_rps *rps)
 	struct drm_i915_private *i915 = rps_to_i915(rps);
 	u32 rpstat;
 
-	if (GRAPHICS_VER(i915) >= 12)
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		rpstat = intel_uncore_read(rps_to_gt(rps)->uncore,
+					   MTL_MIRROR_TARGET_WP1);
+	else if (GRAPHICS_VER(i915) >= 12)
 		rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN12_RPSTAT1);
 	else
 		rpstat = intel_uncore_read(rps_to_gt(rps)->uncore, GEN6_RPSTAT1);
@@ -2060,6 +2063,8 @@  u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
 
 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
 		cagf = (rpstat >> 8) & 0xff;
+	else if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
+		cagf = rpstat & MTL_CAGF_MASK;
 	else if (GRAPHICS_VER(i915) >= 12)
 		cagf = (rpstat & GEN12_CAGF_MASK) >> GEN12_CAGF_SHIFT;
 	else if (GRAPHICS_VER(i915) >= 9)