From patchwork Sat Sep 17 00:43:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 12978927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D0792ECAAD8 for ; Sat, 17 Sep 2022 00:45:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B262F10E0BC; Sat, 17 Sep 2022 00:45:10 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id BCD4A10E028 for ; Sat, 17 Sep 2022 00:44:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663375465; x=1694911465; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cZvuia7A9HKlvE2KLXWlDDdTo3DRQr/kmdMXh9FAIOw=; b=oDU8i5yNUwB+sWcjAUfgP9iRVQzNLocdv4pZjQ1YGdR4iC7NyE6cSMDL NPDG164NyBYy3D7bjeO2XLtdTWQCbgy/uX+WqwDpFeypEJisXYWazyHpW UpmZ87CWAiifkr5Dpf8H5Js2le9U/3TmAoobkUBfsdOSafwHl9qmzrIlK 34/hcqcWtfXTQzJHP8i6u1yNlWGBWLlGY8bCjSjwj0vrkVqoe0CCkPRGG RxHrU1rrgo9rMInoRm8WbGqYo0J2ubVQa/EVNT5Ys3qS70YlcFN1bX1SS J4WciFIvcSNd4LUAqtD0rZGhZ0IZd6p488UG81xBH5PzDrdi3j8J2Xmjl g==; X-IronPort-AV: E=McAfee;i="6500,9779,10472"; a="278835738" X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="278835738" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:25 -0700 X-IronPort-AV: E=Sophos;i="5.93,321,1654585200"; d="scan'208";a="743519280" Received: from cgros-mobl.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.28.3]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Sep 2022 17:44:25 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Fri, 16 Sep 2022 17:43:59 -0700 Message-Id: <20220917004404.414981-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220917004404.414981-1-anusha.srivatsa@intel.com> References: <20220917004404.414981-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/display Add dg2_prog_squash_ctl() helper X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Modularising steps and moving them out of bxt_set_cdclk(). Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 23 +++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index ed05070b7307..220d32adbd12 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1689,6 +1689,18 @@ static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv, return 0xffff; } +static void dg2_prog_squash_ctl(struct drm_i915_private *i915, u16 waveform) +{ + u32 squash_ctl = 0; + + if (waveform) { + squash_ctl |= CDCLK_SQUASH_ENABLE; + squash_ctl |= CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; + } + + intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl); +} + static void bxt_set_cdclk(struct drm_i915_private *dev_priv, const struct intel_cdclk_config *cdclk_config, enum pipe pipe) @@ -1747,15 +1759,8 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv, else clock = cdclk; - if (has_cdclk_squasher(dev_priv)) { - u32 squash_ctl = 0; - - if (waveform) - squash_ctl = CDCLK_SQUASH_ENABLE | - CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform; - - intel_de_write(dev_priv, CDCLK_SQUASH_CTL, squash_ctl); - } + if (has_cdclk_squasher(dev_priv)) + dg2_prog_squash_ctl(dev_priv, waveform); val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) | bxt_cdclk_cd2x_pipe(dev_priv, pipe) |