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[3/4] drm/i915: Add support for GuC tlb invalidation

Message ID 20220921074901.3651252-3-fei.yang@intel.com (mailing list archive)
State New, archived
Headers show
Series [1/4] drm/i915/guc: Define CTB based TLB invalidation routines | expand

Commit Message

Yang, Fei Sept. 21, 2022, 7:49 a.m. UTC 
From: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

When GuC is enabled the tlb invalidations use guc ct otherwise use
mmio interface.

Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Reviewed-by: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Reviewed-by: Fei Yang <fei.yang@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5ddae95d4886..402eec8ba596 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -9,6 +9,7 @@ 
 #include "gem/i915_gem_internal.h"
 #include "gem/i915_gem_lmem.h"
 #include "pxp/intel_pxp.h"
+#include "uc/intel_guc.h"
 
 #include "i915_drv.h"
 #include "i915_perf_oa_regs.h"
@@ -1092,11 +1093,16 @@  void intel_gt_invalidate_tlb(struct intel_gt *gt, u32 seqno)
 		return;
 
 	with_intel_gt_pm_if_awake(gt, wakeref) {
+		struct intel_guc *guc = &gt->uc.guc;
+
 		mutex_lock(&gt->tlb.invalidate_lock);
 		if (tlb_seqno_passed(gt, seqno))
 			goto unlock;
 
-		mmio_invalidate_full(gt);
+		if (INTEL_GUC_SUPPORTS_TLB_INVALIDATION(guc))
+			intel_guc_invalidate_tlb_full(guc, INTEL_GUC_TLB_INVAL_MODE_HEAVY);
+		else
+			mmio_invalidate_full(gt);
 
 		write_seqcount_invalidate(&gt->tlb.seqno);
 unlock: