| Message ID | 20220921105506.2208471-4-suraj.kandpal@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable YCbCr420 for VDSC | expand |
> -----Original Message----- > From: Kandpal, Suraj <suraj.kandpal@intel.com> > Sent: Wednesday, September 21, 2022 4:25 PM > To: intel-gfx@lists.freedesktop.org > Cc: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>; Kulkarni, Vandita > <vandita.kulkarni@intel.com>; Navare, Manasi D > <manasi.d.navare@intel.com>; Kandpal, Suraj <suraj.kandpal@intel.com> > Subject: [PATCH 3/3] drm/i915/display: Fill in native_420 field > > From: Suraj Kandpal <suraj.kandpal@intel.com> > > Now that we have laid the groundwork for YUV420 Enablement we fill up > native_420 field in vdsc_cfg and add appropriate checks wherever required. > > Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> > --- > drivers/gpu/drm/i915/display/icl_dsi.c | 2 -- > drivers/gpu/drm/i915/display/intel_dp.c | 3 --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 16 +++++++++++++++- > 3 files changed, 15 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c > b/drivers/gpu/drm/i915/display/icl_dsi.c > index ed4d93942dbd..9d2710edd27e 100644 > --- a/drivers/gpu/drm/i915/display/icl_dsi.c > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c > @@ -1625,8 +1625,6 @@ static int gen11_dsi_dsc_compute_config(struct > intel_encoder *encoder, > if (crtc_state->dsc.slice_count > 1) > crtc_state->dsc.dsc_split = true; > > - vdsc_cfg->convert_rgb = true; > - > /* FIXME: initialize from VBT */ > vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index f2f77856df83..50ccccf8e121 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1440,9 +1440,6 @@ static int intel_dp_dsc_compute_params(struct > intel_encoder *encoder, > min(intel_dp_source_dsc_version_minor(intel_dp), > intel_dp_sink_dsc_version_minor(intel_dp)); > > - vdsc_cfg->convert_rgb = intel_dp- > >dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & > - DP_DSC_RGB; > - > line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp- > >dsc_dpcd); > if (!line_buf_depth) { > drm_dbg_kms(&i915->drm, > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index a642975a1b61..1ab2a2286c74 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -462,14 +462,28 @@ int intel_dsc_compute_params(struct > intel_crtc_state *pipe_config) > vdsc_cfg->pic_width = pipe_config- > >hw.adjusted_mode.crtc_hdisplay; > vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, > pipe_config->dsc.slice_count); > + /* > + * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb > is 0 > + * else 1 > + */ > + vdsc_cfg->convert_rgb = !(pipe_config->output_format == > INTEL_OUTPUT_FORMAT_YCBCR420 || > + pipe_config->output_format == > INTEL_OUTPUT_FORMAT_YCBCR444); > > - /* Gen 11 does not support YCbCr */ > + if (pipe_config->output_format == > INTEL_OUTPUT_FORMAT_YCBCR420) > + vdsc_cfg->native_420 = true; > + /* Gen 11 does not support YCbCr422 */ > vdsc_cfg->simple_422 = false; From 1.2 onwards we have native_422 as well, so we need to configure it based on the output format. Also, I see that PPS configuration is missing for all 420 and 422 , PPS0 register, please add that. Thanks, Vandita > /* Gen 11 does not support VBR */ > vdsc_cfg->vbr_enable = false; > > /* Gen 11 only supports integral values of bpp */ > vdsc_cfg->bits_per_pixel = compressed_bpp << 4; > + /* > + * According to DSC 1.2 specs if native_420 is set we need to double > the current bpp > + */ > + if (vdsc_cfg->native_420) > + vdsc_cfg->bits_per_pixel <<= 1; > + > vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; > > for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) { > -- > 2.25.1
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index ed4d93942dbd..9d2710edd27e 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1625,8 +1625,6 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, if (crtc_state->dsc.slice_count > 1) crtc_state->dsc.dsc_split = true; - vdsc_cfg->convert_rgb = true; - /* FIXME: initialize from VBT */ vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f2f77856df83..50ccccf8e121 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1440,9 +1440,6 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, min(intel_dp_source_dsc_version_minor(intel_dp), intel_dp_sink_dsc_version_minor(intel_dp)); - vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & - DP_DSC_RGB; - line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); if (!line_buf_depth) { drm_dbg_kms(&i915->drm, diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index a642975a1b61..1ab2a2286c74 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -462,14 +462,28 @@ int intel_dsc_compute_params(struct intel_crtc_state *pipe_config) vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay; vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width, pipe_config->dsc.slice_count); + /* + * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 + * else 1 + */ + vdsc_cfg->convert_rgb = !(pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR444); - /* Gen 11 does not support YCbCr */ + if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + vdsc_cfg->native_420 = true; + /* Gen 11 does not support YCbCr422 */ vdsc_cfg->simple_422 = false; /* Gen 11 does not support VBR */ vdsc_cfg->vbr_enable = false; /* Gen 11 only supports integral values of bpp */ vdsc_cfg->bits_per_pixel = compressed_bpp << 4; + /* + * According to DSC 1.2 specs if native_420 is set we need to double the current bpp + */ + if (vdsc_cfg->native_420) + vdsc_cfg->bits_per_pixel <<= 1; + vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {