| Message ID | 20220922221117.458087-7-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: prepare for uC loading on MTL | expand |
On 9/22/2022 15:11, Daniele Ceraolo Spurio wrote: > The media GT shares the G-unit with the root GT, so a second set of > communication registers is required for the media GuC. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: John Harrison <John.C.Harrison@Intel.com> > Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: John Harrison <John.C.Harrison@Intel.com> > --- > drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++++++++++---- > drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 ++ > 2 files changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > index bac06e3d6f2c..b0beab44b34c 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c > @@ -156,7 +156,8 @@ static void gen11_disable_guc_interrupts(struct intel_guc *guc) > > void intel_guc_init_early(struct intel_guc *guc) > { > - struct drm_i915_private *i915 = guc_to_gt(guc)->i915; > + struct intel_gt *gt = guc_to_gt(guc); > + struct drm_i915_private *i915 = gt->i915; > > intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC); > intel_guc_ct_init_early(&guc->ct); > @@ -168,12 +169,17 @@ void intel_guc_init_early(struct intel_guc *guc) > mutex_init(&guc->send_mutex); > spin_lock_init(&guc->irq_lock); > if (GRAPHICS_VER(i915) >= 11) { > - guc->notify_reg = GEN11_GUC_HOST_INTERRUPT; > guc->interrupts.reset = gen11_reset_guc_interrupts; > guc->interrupts.enable = gen11_enable_guc_interrupts; > guc->interrupts.disable = gen11_disable_guc_interrupts; > - guc->send_regs.base = > - i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); > + if (gt->type == GT_MEDIA) { > + guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT; > + guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0)); > + } else { > + guc->notify_reg = GEN11_GUC_HOST_INTERRUPT; > + guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); > + } > + > guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT; > > } else { > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h > index a7092f711e9c..9915de32e894 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h > @@ -36,6 +36,7 @@ > #define SOFT_SCRATCH_COUNT 16 > > #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4) > +#define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4) > #define GEN11_SOFT_SCRATCH_COUNT 4 > > #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) > @@ -101,6 +102,7 @@ > #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) > #define GUC_SEND_TRIGGER (1<<0) > #define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0) > +#define MEDIA_GUC_HOST_INTERRUPT _MMIO(0x190304) > > #define GEN12_GUC_SEM_INTR_ENABLES _MMIO(0xc71c) > #define GUC_SEM_INTR_ROUTE_TO_GUC BIT(31)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index bac06e3d6f2c..b0beab44b34c 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -156,7 +156,8 @@ static void gen11_disable_guc_interrupts(struct intel_guc *guc) void intel_guc_init_early(struct intel_guc *guc) { - struct drm_i915_private *i915 = guc_to_gt(guc)->i915; + struct intel_gt *gt = guc_to_gt(guc); + struct drm_i915_private *i915 = gt->i915; intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC); intel_guc_ct_init_early(&guc->ct); @@ -168,12 +169,17 @@ void intel_guc_init_early(struct intel_guc *guc) mutex_init(&guc->send_mutex); spin_lock_init(&guc->irq_lock); if (GRAPHICS_VER(i915) >= 11) { - guc->notify_reg = GEN11_GUC_HOST_INTERRUPT; guc->interrupts.reset = gen11_reset_guc_interrupts; guc->interrupts.enable = gen11_enable_guc_interrupts; guc->interrupts.disable = gen11_disable_guc_interrupts; - guc->send_regs.base = - i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); + if (gt->type == GT_MEDIA) { + guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT; + guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0)); + } else { + guc->notify_reg = GEN11_GUC_HOST_INTERRUPT; + guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0)); + } + guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT; } else { diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h index a7092f711e9c..9915de32e894 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h @@ -36,6 +36,7 @@ #define SOFT_SCRATCH_COUNT 16 #define GEN11_SOFT_SCRATCH(n) _MMIO(0x190240 + (n) * 4) +#define MEDIA_SOFT_SCRATCH(n) _MMIO(0x190310 + (n) * 4) #define GEN11_SOFT_SCRATCH_COUNT 4 #define UOS_RSA_SCRATCH(i) _MMIO(0xc200 + (i) * 4) @@ -101,6 +102,7 @@ #define GUC_SEND_INTERRUPT _MMIO(0xc4c8) #define GUC_SEND_TRIGGER (1<<0) #define GEN11_GUC_HOST_INTERRUPT _MMIO(0x1901f0) +#define MEDIA_GUC_HOST_INTERRUPT _MMIO(0x190304) #define GEN12_GUC_SEM_INTR_ENABLES _MMIO(0xc71c) #define GUC_SEM_INTR_ROUTE_TO_GUC BIT(31)
The media GT shares the G-unit with the root GT, so a second set of communication registers is required for the media GuC. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> --- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 14 ++++++++++---- drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h | 2 ++ 2 files changed, 12 insertions(+), 4 deletions(-)