From patchwork Tue Oct 4 10:51:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 12998141 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 42298C433FE for ; Tue, 4 Oct 2022 10:51:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A87AA10E545; Tue, 4 Oct 2022 10:51:41 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id B572810E544 for ; Tue, 4 Oct 2022 10:51:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664880693; x=1696416693; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Pt/olNz85jVKyftkd3e8XYEU02TptBaB8oJTwFAhSm0=; b=W0OodPpiZjtoNUMlWaaxVJfM1D1ZckcsgfmOtUp7jbLKJ4vFjNamQRL5 F4Xa61Z1tr4oTBOVUXOkjN1MaLvkYgTm7wcEu9sVeOHUlZRAP0QZz+x5U DpVMPZy/HwSRu91oQNCTSMHf4Mu39DYruyFbbQWwMIglXNM/3S5qdAipg Eo5QPmGc7cR7TR100bQ0itXOmTmc0aj232fP1l+lklMxPp/PvZYgXiXyu OgQk5sQ7rpmgMM+MrKRpfx/XUyKyXOYUgEznBs3E7e5ubgCwIprGBKcse VJKEJ+kcxWXPozhSQDE31EwKyOURjZsI25Y+zqxujP3jb7qpJ9UGk2GXt w==; X-IronPort-AV: E=McAfee;i="6500,9779,10489"; a="366977486" X-IronPort-AV: E=Sophos;i="5.93,367,1654585200"; d="scan'208";a="366977486" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2022 03:51:33 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10489"; a="749333609" X-IronPort-AV: E=Sophos;i="5.93,367,1654585200"; d="scan'208";a="749333609" Received: from ngverso-mobl2.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.7.149]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2022 03:51:32 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Tue, 4 Oct 2022 11:51:20 +0100 Message-Id: <20221004105121.203149-4-matthew.auld@intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221004105121.203149-1-matthew.auld@intel.com> References: <20221004105121.203149-1-matthew.auld@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 4/5] drm/i915/display: consider DG2_RC_CCS_CC when migrating buffers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Nirmoy Das , Jianshui Yu Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" For these types of display buffers, we need to able to CPU access some part of the backing memory in prepare_plane_clear_colors(). As a result we need to ensure we always place in the mappable part of lmem, which becomes necessary on small-bar systems. v2(Nirmoy & Ville): - Add some commentary for why we need to CPU access the buffer. - Split out the other changes, so we just consider the display change here. v3: - Handle this in the dpt path. Fixes: eb1c535f0d69 ("drm/i915: turn on small BAR support") Reported-by: Jianshui Yu Signed-off-by: Matthew Auld Cc: Ville Syrjälä Cc: Nirmoy Das --- drivers/gpu/drm/i915/display/intel_fb_pin.c | 24 +++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 5031ee5695dd..1aa42862a2c4 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -50,7 +50,18 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, continue; if (HAS_LMEM(dev_priv)) { - ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); + unsigned int flags = obj->flags; + + /* + * For this type of buffer we need to able to read from the CPU + * the clear color value found in the buffer, hence we need to + * ensure it is always in the mappable part of lmem, if this is + * a small-bar device. + */ + if (intel_fb_rc_ccs_cc_plane(fb) >= 0) + flags &= ~I915_BO_ALLOC_GPU_ONLY; + ret = __i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0, + flags); if (ret) continue; } @@ -154,8 +165,17 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, ret = i915_gem_object_lock(obj, &ww); if (!ret && phys_cursor) ret = i915_gem_object_attach_phys(obj, alignment); - else if (!ret && HAS_LMEM(dev_priv)) + else if (!ret && HAS_LMEM(dev_priv)) { + /* + * For this type of ccs buffer we need to able to read from the + * CPU the clear color value found in the buffer, which might + * require moving to the mappable part of lmem first, but here + * we should be using dpt for this. + */ + WARN_ON_ONCE(intel_fb_rc_ccs_cc_plane(fb) >= 0); + ret = i915_gem_object_migrate(obj, &ww, INTEL_REGION_LMEM_0); + } if (!ret) ret = i915_gem_object_pin_pages(obj); if (ret)