From patchwork Wed Nov 2 17:45:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Hogander, Jouni" X-Patchwork-Id: 13028706 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C1C3FC433FE for ; Wed, 2 Nov 2022 17:46:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B2F1510E516; Wed, 2 Nov 2022 17:46:18 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 90B9310E516 for ; Wed, 2 Nov 2022 17:46:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667411175; x=1698947175; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QcnZQD7ImLP7g8vm/bRdk82H4ZfLkN/ncJownF0RlP8=; b=n2kfmJ21Poc1Lx7hGjfPQvzLMCwgBD6X3vDNMVwKpZMdQWE4bBGvMbbM I0IfSVPRn2ikIFU0KiLjmZbZXN1lYzl9rzNRN58nkkLs5wBXhMB7wfj7V UqclsOjhbCTVQDL2BkA6n9mMhNQuAenFTx4Qv940KCRJnaYMtqqgz2yi6 0aPJiY/0GXFVlViU8eHLdKVVCwjMLLtjzIuS1SGXv3wXVpCdpUjD5ZDal a84rXrU9lcHzDkYVjNejMhRi9BbfDocNoTcvZdubRzUwxcw5DAnxclx1j MqojTLrqEHK4qkRGIyV/h6apJbTeT2/TPhqfThWJ/XDsFFljsnhpBFLYf w==; X-IronPort-AV: E=McAfee;i="6500,9779,10519"; a="308197950" X-IronPort-AV: E=Sophos;i="5.95,234,1661842800"; d="scan'208";a="308197950" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 10:46:00 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10519"; a="759640267" X-IronPort-AV: E=Sophos;i="5.95,234,1661842800"; d="scan'208";a="759640267" Received: from asridha2-mobl.gar.corp.intel.com (HELO jhogande-mobl1.ger.corp.intel.com) ([10.251.216.192]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Nov 2022 10:45:59 -0700 From: =?utf-8?q?Jouni_H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org Date: Wed, 2 Nov 2022 19:45:43 +0200 Message-Id: <20221102174544.2288205-2-jouni.hogander@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221102174544.2288205-1-jouni.hogander@intel.com> References: <20221102174544.2288205-1-jouni.hogander@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Subject: [Intel-gfx] [PATCH 1/2] drm/i915/psr: Ensure panel granularity aligns with DSC slice height X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Do not enable psr2 if panel ganularity is not aligned with DSC slice height when DSC is enabled Cc: José Roberto de Souza Cc: Mika Kahola Signed-off-by: Jouni Högander Reviewed-by: José Roberto de Souza Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/display/intel_psr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e11b0592055f..57575b5c6d48 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -779,6 +779,7 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; u16 y_granularity = 0; @@ -809,6 +810,10 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp, if (y_granularity == 0 || crtc_vdisplay % y_granularity) return false; + if (crtc_state->dsc.compression_enable && + vdsc_cfg->slice_height % y_granularity) + return false; + crtc_state->su_y_granularity = y_granularity; return true; }