From patchwork Mon Nov 7 07:26:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kandpal, Suraj" X-Patchwork-Id: 13033964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11540C43219 for ; Mon, 7 Nov 2022 07:27:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A9A310E24F; Mon, 7 Nov 2022 07:27:37 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id D5DAE10E248 for ; Mon, 7 Nov 2022 07:27:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667806041; x=1699342041; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2bRvokPd3+ZdOASFjNa6AOH9Xt+ClhX27QvvUMvjPVY=; b=YekLWX+jXU8Jg293GJ+xguub1Kcus+WUi0gNWZWY5tiMtBwiOTD0Wnwk fZ5maZpuS04XDTDfYUz1xL9sEG2J16dQxtqiA0h6qj3zqDgetr98Nw4yr ZIJtMkE25TFWupdTC/F32GpC/N0eHx80iCaLNgOl8Bf5O50FAC+llqrBl K0g8nScfOwFxvf0iZdmNnqrFSLwk1JDZUD2giP2weahgipk4dBBVwBz8a qxIqOLhSMmwVs/Wxq2wZKystIXSl3Y035W7AgMycz/l4CcycKdztAcwnS q4YCJL0HuhXMMhfxPXDWFhOeM10lrT74SgHU6Zz0HBaoy24U/QVjU2x6X w==; X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="311479917" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="311479917" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2022 23:27:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="880962006" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="880962006" Received: from kandpal-x299-ud4-pro.iind.intel.com ([10.190.239.32]) by fmsmga006.fm.intel.com with ESMTP; 06 Nov 2022 23:27:20 -0800 From: Suraj Kandpal To: intel-gfx@lists.freedesktop.org Date: Mon, 7 Nov 2022 12:56:09 +0530 Message-Id: <20221107072615.1352929-3-suraj.kandpal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221107072615.1352929-1-suraj.kandpal@intel.com> References: <20221014152622.233398-1-suraj.kandpal@intel.com> <20221107072615.1352929-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 2/8] drm/i915/dp: Check if DSC supports the given output_format X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ankit Nautiyal Go with DSC only if the given output_format is supported. v2: Use drm helper to get DSC format support for sink. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7400d6b4c587..a5c31ac1ec73 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1464,6 +1464,31 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } +static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, + enum intel_output_format output_format) +{ + u8 sink_dsc_format; + + switch (output_format) { + case INTEL_OUTPUT_FORMAT_RGB: + sink_dsc_format = DP_DSC_RGB; + break; + case INTEL_OUTPUT_FORMAT_YCBCR444: + sink_dsc_format = DP_DSC_YCbCr444; + break; + case INTEL_OUTPUT_FORMAT_YCBCR420: + if (min(intel_dp_source_dsc_version_minor(intel_dp), + intel_dp_sink_dsc_version_minor(intel_dp)) < 2) + return false; + sink_dsc_format = DP_DSC_YCbCr420_Native; + break; + default: + return false; + } + + return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); +} + static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1482,6 +1507,9 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_supports_dsc(intel_dp, pipe_config)) return -EINVAL; + if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) + return -EINVAL; + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); if (intel_dp->force_dsc_bpc) {