From patchwork Thu Nov 10 05:37:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 13038290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9286AC4332F for ; Thu, 10 Nov 2022 05:37:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6FAA510E09E; Thu, 10 Nov 2022 05:37:13 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44D2510E09E for ; Thu, 10 Nov 2022 05:37:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668058631; x=1699594631; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=VSv24uZyaRo7nf1ucQLOw6k2k0hi1GqNxB9WrzXQTS8=; b=EDj++QYvGbs+HlH2lZANLtevK+w8g+jtK4MkY2pyL8mHSCo+M7HbfWKE hFEslxUBvbB9arjTg2mB0IZWl04MDc73Xf1+0qXYdPJqj+s2zXbZ37R4G uxsp42xJk3V1i08La8yeKtCfWhrWRnBxaXucbv29kkBSGof6JL7yk9MdW oZ0i7zW2GEx6avx/JzTvSTwG6/S1HsAasjKjd+s5AAqK4KztjpKRDrH3V /nKixx33F0dDWBt6GKqS01ZYLp8kIq8AJ2pLvH/m4dqU1K1TZJNHE3Fyx mDZE7rhsZ3kcV5jwOiuPNTBNrkb/dpyvGRZkURvudVktDUgPSpWo2h2/r g==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="375463256" X-IronPort-AV: E=Sophos;i="5.96,152,1665471600"; d="scan'208";a="375463256" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 21:37:10 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="762153258" X-IronPort-AV: E=Sophos;i="5.96,152,1665471600"; d="scan'208";a="762153258" Received: from mdatla-mobl1.amr.corp.intel.com (HELO anushasr-mobl7.intel.com) ([10.209.100.94]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 21:37:10 -0800 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Wed, 9 Nov 2022 21:37:24 -0800 Message-Id: <20221110053724.14701-1-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH] drm/i915/display: Add missing checks for cdclk crawling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" cdclk_sanitize() function was written assuming vco was a signed integer. vco gets assigned to -1 (essentially ~0) for the case where PLL might be enabled and vco is not a frequency that will ever get used. In such a scenario the right thing to do is disable the PLL and re-enable it again with a valid frequency. However the vco is declared as a unsigned variable. With the above assumption, driver takes crawl path when not needed. Add explicit check to not crawl in the case of an invalid PLL. Cc: Matt Roper Suggested-by: Ville Syrjälä Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 ++ drivers/gpu/drm/i915/display/intel_cdclk.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 8a9031012d74..91112d266763 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1962,6 +1962,8 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv, if (!HAS_CDCLK_CRAWL(dev_priv)) return false; + if (intel_pll_is_unknown(a->vco)) + return false; /* * The vco and cd2x divider will change independently * from each, so we disallow cd2x change when crawling. diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h index c674879a84a5..6eb83d806f11 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.h +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h @@ -80,6 +80,7 @@ intel_atomic_get_cdclk_state(struct intel_atomic_state *state); to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj)) #define intel_atomic_get_new_cdclk_state(state) \ to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->display.cdclk.obj)) +#define intel_pll_is_unknown(vco) ((vco) == ~0) int intel_cdclk_init(struct drm_i915_private *dev_priv);