| Message ID | 20221117192204.445428-1-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Skip doubling channel numbers for LPDDR4/LPDDDR5 | expand |
On Thu, Nov 17, 2022 at 11:22:04AM -0800, Radhakrishna Sripada wrote: > MTL LPDDR5 reported 16b with 8 channels. Previous platforms > reported 32b with 4 channels and hence needed a mulitplication > by a factor of 2. Skip increasing the channels for MTL. Looks like the bspec was just updated a couple weeks ago with this change. > > While at it fix the logic while reading dram info num channels. It's probably better to break this out into its own patch since it's an independent bugfix, not related to the last month's bspec update. > > Bspec: 64631 > Fixes: 825477e77912 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox") > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bw.c | 3 ++- > drivers/gpu/drm/i915/intel_dram.c | 3 +-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index 4ace026b29bd..7601e1061bca 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -439,7 +439,8 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel > return ret; > } > > - if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5) > + if (!IS_METEORLAKE(dev_priv) && Unless we have a reason to believe otherwise, we should assume that this change will carry forward to future platforms as well, so this should be a version check rather than specifically checking IS_METEORLAKE. Matt > + (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5)) > num_channels *= 2; > > qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); > diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c > index 2403ccd52c74..bba8cb6e8ae4 100644 > --- a/drivers/gpu/drm/i915/intel_dram.c > +++ b/drivers/gpu/drm/i915/intel_dram.c > @@ -471,8 +471,7 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) > u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); > struct dram_info *dram_info = &i915->dram_info; > > - val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val); > - switch (val) { > + switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { > case 0: > dram_info->type = INTEL_DRAM_DDR4; > break; > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 4ace026b29bd..7601e1061bca 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -439,7 +439,8 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel return ret; } - if (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5) + if (!IS_METEORLAKE(dev_priv) && + (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5)) num_channels *= 2; qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2); diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c index 2403ccd52c74..bba8cb6e8ae4 100644 --- a/drivers/gpu/drm/i915/intel_dram.c +++ b/drivers/gpu/drm/i915/intel_dram.c @@ -471,8 +471,7 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); struct dram_info *dram_info = &i915->dram_info; - val = REG_FIELD_GET(MTL_DDR_TYPE_MASK, val); - switch (val) { + switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) { case 0: dram_info->type = INTEL_DRAM_DDR4; break;
MTL LPDDR5 reported 16b with 8 channels. Previous platforms reported 32b with 4 channels and hence needed a mulitplication by a factor of 2. Skip increasing the channels for MTL. While at it fix the logic while reading dram info num channels. Bspec: 64631 Fixes: 825477e77912 ("drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox") Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/display/intel_bw.c | 3 ++- drivers/gpu/drm/i915/intel_dram.c | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-)