| Message ID | 20221123235342.713068-1-umesh.nerlige.ramappa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] drm/i915/perf: Do not parse context image for HSW | expand |
On Tue, Nov 29, 2022 at 07:19:11AM +0000, Patchwork wrote: > Patch Details > >Series: drm/i915/perf: Do not parse context image for HSW (rev4) >URL: [1]https://patchwork.freedesktop.org/series/111231/ >State: failure >Details: [2]https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_111231v4/index.html > > CI Bug Log - changes from CI_DRM_12440_full -> Patchwork_111231v4_full > >Summary > > FAILURE > > Serious unknown changes coming with Patchwork_111231v4_full absolutely > need to be > verified manually. > > If you think the reported changes have nothing to do with the changes > introduced in Patchwork_111231v4_full, please notify your bug team to > allow them > to document this new failure mode, which will reduce false positives in > CI. > >Participating hosts (10 -> 10) > > No changes in participating hosts > >Possible new issues > > Here are the unknown changes that may have been introduced in > Patchwork_111231v4_full: > > IGT changes > > Possible regressions > > * igt@gem_mmap_offset@open-flood: > > * shard-skl: [3]PASS -> [4]INCOMPLETE This is unrelated since the changes in this patch are localized to a very specific OA use case. The above test does not exercise this path. Umesh > >Known issues
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 00e09bb18b13..125b6ca25a75 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1383,6 +1383,9 @@ static u32 oa_context_image_offset(struct intel_context *ce, u32 reg) u32 offset, len = (ce->engine->context_size - PAGE_SIZE) / 4; u32 *state = ce->lrc_reg_state; + if (drm_WARN_ON(&ce->engine->i915->drm, !state)) + return U32_MAX; + for (offset = 0; offset < len; ) { if (IS_MI_LRI_CMD(state[offset])) { /* @@ -1447,7 +1450,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) if (IS_ERR(ce)) return PTR_ERR(ce); - if (engine_supports_mi_query(stream->engine)) { + if (engine_supports_mi_query(stream->engine) && + HAS_LOGICAL_RING_CONTEXTS(stream->perf->i915)) { /* * We are enabling perf query here. If we don't find the context * offset here, just return an error.
An earlier commit introduced a mechanism to parse the context image to find the OA context control offset. This resulted in an NPD on haswell when gem_context was passed into i915_perf_open_ioctl params. Haswell does not support logical ring contexts, so ensure that the context image is parsed only for platforms with logical ring contexts and also validate lrc_reg_state. v2: Fix build failure v3: Fix checkpatch error Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7432 Fixes: a5c3a3cbf029 ("drm/i915/perf: Determine gen12 oa ctx offset at runtime") Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-)