diff mbox series

[v2,1/4] drm/i915/mtl: Resize noa_wait BO size to save restore GPR regs

Message ID 20221201010535.1097741-2-umesh.nerlige.ramappa@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915/mtl: Add OAG 32 bit format support for MTL | expand

Commit Message

Umesh Nerlige Ramappa Dec. 1, 2022, 1:05 a.m. UTC 
On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
caused a hang that was attributed to saving and restoring the GPR
registers used for noa_wait.

Add an additional page in noa_wait BO to save/restore GPR registers for
the noa_wait logic.

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_gt_types.h |  6 ------
 drivers/gpu/drm/i915/i915_perf.c         | 25 ++++++++++++++++--------
 2 files changed, 17 insertions(+), 14 deletions(-)

Comments

Dixit, Ashutosh Dec. 1, 2022, 2:18 a.m. UTC | #1 
On Wed, 30 Nov 2022 17:05:32 -0800, Umesh Nerlige Ramappa wrote:
>
> On MTL, gt->scratch was using stolen lmem. An MI_SRM to stolen lmem
> caused a hang that was attributed to saving and restoring the GPR
> registers used for noa_wait.
>
> Add an additional page in noa_wait BO to save/restore GPR registers for
> the noa_wait logic.

Mostly copying R-b's from https://patchwork.freedesktop.org/series/111411/ here.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_types.h |  6 ------
>  drivers/gpu/drm/i915/i915_perf.c         | 25 ++++++++++++++++--------
>  2 files changed, 17 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index c1d9cd255e06..13dffe0a3d20 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -296,12 +296,6 @@ enum intel_gt_scratch_field {
>
>	/* 8 bytes */
>	INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
> -
> -	/* 6 * 8 bytes */
> -	INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
> -
> -	/* 4 bytes */
> -	INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
>  };
>
>  #endif /* __INTEL_GT_TYPES_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 00e09bb18b13..7790a88f10d8 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1842,8 +1842,7 @@ static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
>	for (d = 0; d < dword_count; d++) {
>		*cs++ = cmd;
>		*cs++ = i915_mmio_reg_offset(reg) + 4 * d;
> -		*cs++ = intel_gt_scratch_offset(stream->engine->gt,
> -						offset) + 4 * d;
> +		*cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
>		*cs++ = 0;
>	}
>
> @@ -1876,7 +1875,13 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>					  MI_PREDICATE_RESULT_2_ENGINE(base) :
>					  MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
>
> -	bo = i915_gem_object_create_internal(i915, 4096);
> +	/*
> +	 * gt->scratch was being used to save/restore the GPR registers, but on
> +	 * MTL the scratch uses stolen lmem. An MI_SRM to this memory region
> +	 * causes an engine hang. Instead allocate an additional page here to
> +	 * save/restore GPR registers
> +	 */
> +	bo = i915_gem_object_create_internal(i915, 8192);
>	if (IS_ERR(bo)) {
>		drm_err(&i915->drm,
>			"Failed to allocate NOA wait batchbuffer\n");
> @@ -1910,14 +1915,19 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>		goto err_unpin;
>	}
>
> +	stream->noa_wait = vma;
> +
> +#define GPR_SAVE_OFFSET 4096
> +#define PREDICATE_SAVE_OFFSET 4160
> +
>	/* Save registers. */
>	for (i = 0; i < N_CS_GPR; i++)
>		cs = save_restore_register(
>			stream, cs, true /* save */, CS_GPR(i),
> -			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
> +			GPR_SAVE_OFFSET + 8 * i, 2);
>	cs = save_restore_register(
>		stream, cs, true /* save */, mi_predicate_result,
> -		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
> +		PREDICATE_SAVE_OFFSET, 1);
>
>	/* First timestamp snapshot location. */
>	ts0 = cs;
> @@ -2033,10 +2043,10 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>	for (i = 0; i < N_CS_GPR; i++)
>		cs = save_restore_register(
>			stream, cs, false /* restore */, CS_GPR(i),
> -			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
> +			GPR_SAVE_OFFSET + 8 * i, 2);
>	cs = save_restore_register(
>		stream, cs, false /* restore */, mi_predicate_result,
> -		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
> +		PREDICATE_SAVE_OFFSET, 1);
>
>	/* And return to the ring. */
>	*cs++ = MI_BATCH_BUFFER_END;
> @@ -2046,7 +2056,6 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
>	i915_gem_object_flush_map(bo);
>	__i915_gem_object_release_map(bo);
>
> -	stream->noa_wait = vma;
>	goto out_ww;
>
>  err_unpin:
> --
> 2.36.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index c1d9cd255e06..13dffe0a3d20 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -296,12 +296,6 @@  enum intel_gt_scratch_field {
 
 	/* 8 bytes */
 	INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
-
-	/* 6 * 8 bytes */
-	INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
-
-	/* 4 bytes */
-	INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
 };
 
 #endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 00e09bb18b13..7790a88f10d8 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1842,8 +1842,7 @@  static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
 	for (d = 0; d < dword_count; d++) {
 		*cs++ = cmd;
 		*cs++ = i915_mmio_reg_offset(reg) + 4 * d;
-		*cs++ = intel_gt_scratch_offset(stream->engine->gt,
-						offset) + 4 * d;
+		*cs++ = i915_ggtt_offset(stream->noa_wait) + offset + 4 * d;
 		*cs++ = 0;
 	}
 
@@ -1876,7 +1875,13 @@  static int alloc_noa_wait(struct i915_perf_stream *stream)
 					  MI_PREDICATE_RESULT_2_ENGINE(base) :
 					  MI_PREDICATE_RESULT_1(RENDER_RING_BASE);
 
-	bo = i915_gem_object_create_internal(i915, 4096);
+	/*
+	 * gt->scratch was being used to save/restore the GPR registers, but on
+	 * MTL the scratch uses stolen lmem. An MI_SRM to this memory region
+	 * causes an engine hang. Instead allocate an additional page here to
+	 * save/restore GPR registers
+	 */
+	bo = i915_gem_object_create_internal(i915, 8192);
 	if (IS_ERR(bo)) {
 		drm_err(&i915->drm,
 			"Failed to allocate NOA wait batchbuffer\n");
@@ -1910,14 +1915,19 @@  static int alloc_noa_wait(struct i915_perf_stream *stream)
 		goto err_unpin;
 	}
 
+	stream->noa_wait = vma;
+
+#define GPR_SAVE_OFFSET 4096
+#define PREDICATE_SAVE_OFFSET 4160
+
 	/* Save registers. */
 	for (i = 0; i < N_CS_GPR; i++)
 		cs = save_restore_register(
 			stream, cs, true /* save */, CS_GPR(i),
-			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+			GPR_SAVE_OFFSET + 8 * i, 2);
 	cs = save_restore_register(
 		stream, cs, true /* save */, mi_predicate_result,
-		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+		PREDICATE_SAVE_OFFSET, 1);
 
 	/* First timestamp snapshot location. */
 	ts0 = cs;
@@ -2033,10 +2043,10 @@  static int alloc_noa_wait(struct i915_perf_stream *stream)
 	for (i = 0; i < N_CS_GPR; i++)
 		cs = save_restore_register(
 			stream, cs, false /* restore */, CS_GPR(i),
-			INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+			GPR_SAVE_OFFSET + 8 * i, 2);
 	cs = save_restore_register(
 		stream, cs, false /* restore */, mi_predicate_result,
-		INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+		PREDICATE_SAVE_OFFSET, 1);
 
 	/* And return to the ring. */
 	*cs++ = MI_BATCH_BUFFER_END;
@@ -2046,7 +2056,6 @@  static int alloc_noa_wait(struct i915_perf_stream *stream)
 	i915_gem_object_flush_map(bo);
 	__i915_gem_object_release_map(bo);
 
-	stream->noa_wait = vma;
 	goto out_ww;
 
 err_unpin: