From patchwork Mon Jan 2 06:20:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Borah, Chaitanya Kumar" X-Patchwork-Id: 13086544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 884C9C4167B for ; Mon, 2 Jan 2023 06:20:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 426FE10E18A; Mon, 2 Jan 2023 06:20:17 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id CBA4010E0CC for ; Mon, 2 Jan 2023 06:20:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1672640413; x=1704176413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z+ofmlmt/BsCW8VCe6+BRYbH5eHuR/1UMtdZJnGjrwo=; b=VQaPRZeV2KAUa+eAQjQnltuAX3dIcY5hzRLkiMWByPx3ZiK1eigkXLRd MDiVV1ph1Iw1gINFqjGXJpyMe1PlEeopEC+wO+y2rx46CaJf5N5ZagfNz vfGFEa2CIT5CDls6h6lvI/NGeLb6d7DG4Qr5/TDcRjXIdwTlmni7MWKS7 CAbO6v/rj/2RVW880TEC+nOe3ZDeWhW//1qdCr1iA41/7tzo7wxapBtNm 2SyTyIaeG/vlONOhpBIShUaFMc9Jwe/oIiNCQPVdcv6VoCq9MuWS6nrCw GDrK1lQWH16r89tzZeKHnbEQykI0zUpHLguE65U2e2G6CokMbX95GS9KM A==; X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="348657600" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="348657600" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jan 2023 22:20:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10577"; a="647840548" X-IronPort-AV: E=Sophos;i="5.96,293,1665471600"; d="scan'208";a="647840548" Received: from chaitanya.iind.intel.com ([10.190.239.113]) by orsmga007.jf.intel.com with ESMTP; 01 Jan 2023 22:20:11 -0800 From: Chaitanya Kumar Borah To: intel-gfx@lists.freedesktop.org Date: Mon, 2 Jan 2023 11:50:02 +0530 Message-Id: <20230102062005.720964-2-chaitanya.kumar.borah@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> References: <20230102062005.720964-1-chaitanya.kumar.borah@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC 1/4] drm/i915/quirks: Add quirk for 480MHz CDCLK step X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ville.syrjala@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" A new CDCLK step of 480MHz has been added on SKUs that has a RPL-U device id. This is done to support 120Hz displays with more efficiency. RPL-U device ids are currently added within the RPL-P sub platform. It seems to be an overkill to add a separate sub platform just to support this change. Therefore, quirks are a good way to achieve the same. BSpec: 55409 Signed-off-by: Chaitanya Kumar Borah --- drivers/gpu/drm/i915/display/intel_quirks.c | 14 ++++++++++++++ drivers/gpu/drm/i915/display/intel_quirks.h | 1 + 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_quirks.c b/drivers/gpu/drm/i915/display/intel_quirks.c index 6e48d3bcdfec..0a30499835b3 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.c +++ b/drivers/gpu/drm/i915/display/intel_quirks.c @@ -65,6 +65,16 @@ static void quirk_no_pps_backlight_power_hook(struct drm_i915_private *i915) drm_info(&i915->drm, "Applying no pps backlight power quirk\n"); } +/* + * A new step of 480MHz has been added on SKUs that have a RPL-U device id. + * This particular step is to better support 120Hz panels. + */ +static void quirk_480mhz_cdclk_step_hook(struct drm_i915_private *i915) +{ + intel_set_quirk(i915, QUIRK_480MHZ_CDCLK_STEP); + drm_info(&i915->drm, "Applying 480MHz CDCLK step quirk\n"); +} + struct intel_quirk { int device; int subsystem_vendor; @@ -199,6 +209,10 @@ static struct intel_quirk intel_quirks[] = { /* ECS Liva Q2 */ { 0x3185, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time }, { 0x3184, 0x1019, 0xa94d, quirk_increase_ddi_disabled_time }, + /* RPL-U */ + { 0xA7A1, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook }, + { 0xA721, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook }, + { 0xA7A9, PCI_ANY_ID, PCI_ANY_ID, quirk_480mhz_cdclk_step_hook }, }; void intel_init_quirks(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/display/intel_quirks.h b/drivers/gpu/drm/i915/display/intel_quirks.h index 10a4d163149f..71e05684f5f4 100644 --- a/drivers/gpu/drm/i915/display/intel_quirks.h +++ b/drivers/gpu/drm/i915/display/intel_quirks.h @@ -17,6 +17,7 @@ enum intel_quirk_id { QUIRK_INVERT_BRIGHTNESS, QUIRK_LVDS_SSC_DISABLE, QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK, + QUIRK_480MHZ_CDCLK_STEP, }; void intel_init_quirks(struct drm_i915_private *i915);