diff mbox series

[v2,5/9] drm/i915/display/pch: use intel_de_rmw if possible

Message ID 20230105131046.2173431-5-andrzej.hajda@intel.com (mailing list archive)
State New, archived
Headers show
Series [v2,1/9] drm/i915/display/core: use intel_de_rmw if possible | expand

Commit Message

Andrzej Hajda Jan. 5, 2023, 1:10 p.m. UTC 
The helper makes the code more compact and readable.

Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
 .../gpu/drm/i915/display/intel_pch_display.c  | 41 +++++--------------
 .../gpu/drm/i915/display/intel_pch_refclk.c   | 10 +----
 2 files changed, 13 insertions(+), 38 deletions(-)

Comments

Rodrigo Vivi Jan. 6, 2023, 3:28 p.m. UTC | #1 
On Thu, Jan 05, 2023 at 02:10:42PM +0100, Andrzej Hajda wrote:
> The helper makes the code more compact and readable.
> 
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_pch_display.c  | 41 +++++--------------
>  .../gpu/drm/i915/display/intel_pch_refclk.c   | 10 +----
>  2 files changed, 13 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index cecc0d007cf39c..4b5e069a1b9051 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -307,7 +307,6 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	i915_reg_t reg;
> -	u32 val;
>  
>  	/* FDI relies on the transcoder */
>  	assert_fdi_tx_disabled(dev_priv, pipe);
> @@ -317,21 +316,16 @@ static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
>  	assert_pch_ports_disabled(dev_priv, pipe);
>  
>  	reg = PCH_TRANSCONF(pipe);
> -	val = intel_de_read(dev_priv, reg);
> -	val &= ~TRANS_ENABLE;
> -	intel_de_write(dev_priv, reg, val);
> +	intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0);
>  	/* wait for PCH transcoder off, transcoder state */
>  	if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
>  		drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
>  			pipe_name(pipe));
>  
> -	if (HAS_PCH_CPT(dev_priv)) {
> +	if (HAS_PCH_CPT(dev_priv))
>  		/* Workaround: Clear the timing override chicken bit again. */
> -		reg = TRANS_CHICKEN2(pipe);
> -		val = intel_de_read(dev_priv, reg);
> -		val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> -		intel_de_write(dev_priv, reg, val);
> -	}
> +		intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe),
> +			     TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
>  }
>  
>  void ilk_pch_pre_enable(struct intel_atomic_state *state,
> @@ -456,21 +450,14 @@ void ilk_pch_post_disable(struct intel_atomic_state *state,
>  	ilk_disable_pch_transcoder(crtc);
>  
>  	if (HAS_PCH_CPT(dev_priv)) {
> -		i915_reg_t reg;
> -		u32 temp;
> -
>  		/* disable TRANS_DP_CTL */
> -		reg = TRANS_DP_CTL(pipe);
> -		temp = intel_de_read(dev_priv, reg);
> -		temp &= ~(TRANS_DP_OUTPUT_ENABLE |
> -			  TRANS_DP_PORT_SEL_MASK);
> -		temp |= TRANS_DP_PORT_SEL_NONE;
> -		intel_de_write(dev_priv, reg, temp);
> +		intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe),
> +			     TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK,
> +			     TRANS_DP_PORT_SEL_NONE);
>  
>  		/* disable DPLL_SEL */
> -		temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
> -		temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
> -		intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
> +		intel_de_rmw(dev_priv, PCH_DPLL_SEL,
> +			     TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);
>  	}
>  
>  	ilk_fdi_pll_disable(crtc);
> @@ -580,20 +567,14 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>  
>  static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
>  {
> -	u32 val;
> -
> -	val = intel_de_read(dev_priv, LPT_TRANSCONF);
> -	val &= ~TRANS_ENABLE;
> -	intel_de_write(dev_priv, LPT_TRANSCONF, val);
> +	intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0);
>  	/* wait for PCH transcoder off, transcoder state */
>  	if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
>  				    TRANS_STATE_ENABLE, 50))
>  		drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
>  
>  	/* Workaround: clear timing override bit. */
> -	val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
> -	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
> -	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
> +	intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
>  }
>  
>  void lpt_pch_enable(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> index 08a94365b7d13b..6780c8fd9a1d31 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
> @@ -12,19 +12,13 @@
>  
>  static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
>  {
> -	u32 tmp;
> -
> -	tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
> -	tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
> -	intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
> +	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
>  
>  	if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
>  			FDI_MPHY_IOSFSB_RESET_STATUS, 100))
>  		drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
>  
> -	tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
> -	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
> -	intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
> +	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
>  
>  	if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
>  			 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
> -- 
> 2.34.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index cecc0d007cf39c..4b5e069a1b9051 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -307,7 +307,6 @@  static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	i915_reg_t reg;
-	u32 val;
 
 	/* FDI relies on the transcoder */
 	assert_fdi_tx_disabled(dev_priv, pipe);
@@ -317,21 +316,16 @@  static void ilk_disable_pch_transcoder(struct intel_crtc *crtc)
 	assert_pch_ports_disabled(dev_priv, pipe);
 
 	reg = PCH_TRANSCONF(pipe);
-	val = intel_de_read(dev_priv, reg);
-	val &= ~TRANS_ENABLE;
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0);
 	/* wait for PCH transcoder off, transcoder state */
 	if (intel_de_wait_for_clear(dev_priv, reg, TRANS_STATE_ENABLE, 50))
 		drm_err(&dev_priv->drm, "failed to disable transcoder %c\n",
 			pipe_name(pipe));
 
-	if (HAS_PCH_CPT(dev_priv)) {
+	if (HAS_PCH_CPT(dev_priv))
 		/* Workaround: Clear the timing override chicken bit again. */
-		reg = TRANS_CHICKEN2(pipe);
-		val = intel_de_read(dev_priv, reg);
-		val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
-		intel_de_write(dev_priv, reg, val);
-	}
+		intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe),
+			     TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
 }
 
 void ilk_pch_pre_enable(struct intel_atomic_state *state,
@@ -456,21 +450,14 @@  void ilk_pch_post_disable(struct intel_atomic_state *state,
 	ilk_disable_pch_transcoder(crtc);
 
 	if (HAS_PCH_CPT(dev_priv)) {
-		i915_reg_t reg;
-		u32 temp;
-
 		/* disable TRANS_DP_CTL */
-		reg = TRANS_DP_CTL(pipe);
-		temp = intel_de_read(dev_priv, reg);
-		temp &= ~(TRANS_DP_OUTPUT_ENABLE |
-			  TRANS_DP_PORT_SEL_MASK);
-		temp |= TRANS_DP_PORT_SEL_NONE;
-		intel_de_write(dev_priv, reg, temp);
+		intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe),
+			     TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK,
+			     TRANS_DP_PORT_SEL_NONE);
 
 		/* disable DPLL_SEL */
-		temp = intel_de_read(dev_priv, PCH_DPLL_SEL);
-		temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
-		intel_de_write(dev_priv, PCH_DPLL_SEL, temp);
+		intel_de_rmw(dev_priv, PCH_DPLL_SEL,
+			     TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe), 0);
 	}
 
 	ilk_fdi_pll_disable(crtc);
@@ -580,20 +567,14 @@  static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
 
 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
 {
-	u32 val;
-
-	val = intel_de_read(dev_priv, LPT_TRANSCONF);
-	val &= ~TRANS_ENABLE;
-	intel_de_write(dev_priv, LPT_TRANSCONF, val);
+	intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0);
 	/* wait for PCH transcoder off, transcoder state */
 	if (intel_de_wait_for_clear(dev_priv, LPT_TRANSCONF,
 				    TRANS_STATE_ENABLE, 50))
 		drm_err(&dev_priv->drm, "Failed to disable PCH transcoder\n");
 
 	/* Workaround: clear timing override bit. */
-	val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A));
-	val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
-	intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
+	intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0);
 }
 
 void lpt_pch_enable(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 08a94365b7d13b..6780c8fd9a1d31 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -12,19 +12,13 @@ 
 
 static void lpt_fdi_reset_mphy(struct drm_i915_private *dev_priv)
 {
-	u32 tmp;
-
-	tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
-	tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
-	intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
+	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
 
 	if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) &
 			FDI_MPHY_IOSFSB_RESET_STATUS, 100))
 		drm_err(&dev_priv->drm, "FDI mPHY reset assert timeout\n");
 
-	tmp = intel_de_read(dev_priv, SOUTH_CHICKEN2);
-	tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
-	intel_de_write(dev_priv, SOUTH_CHICKEN2, tmp);
+	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
 
 	if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) &
 			 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))