From patchwork Wed Jan 11 23:55:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13097309 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0452FC46467 for ; Wed, 11 Jan 2023 23:56:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6ABAE10E841; Wed, 11 Jan 2023 23:56:26 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 17D0B10E176 for ; Wed, 11 Jan 2023 23:56:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673481376; x=1705017376; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VeEEMEfaDJi7WipJm4u0djyub4z8+tTttj8kY2PiqJk=; b=HrB5NCUuUwh63L/BEmFM+S302yYR68pQGwZ9z5mEjozcwI0ZHzjG3MZO Chv4b7K2I9rasRza+PeO1loJV8U+RuV8ddMoHv87eNr7Y39Q7GBGvUIKS WJadbeBGkhY4r30wAGfuR90MCkXUqyZL/BjZNZpxT86dlL2/Iz5yE+m9P 0v6wv/V/S8FaQOXj8JBgg8kZQh/AHatCZnAQi+DuLgrCkChhRqgA+N5Kg EZS3JYWJrsB30SpL/aui86ZwolOP5zfUjAbJ0jlLdMaMM5yyzZ4BXERFQ HvYKeUiwlaZUKZvuSFXinyVsGEb+KLYLKEy384VGfzwmcNi8T9DvVki5O Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="307090897" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="307090897" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10586"; a="831486376" X-IronPort-AV: E=Sophos;i="5.96,318,1665471600"; d="scan'208";a="831486376" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jan 2023 15:56:14 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Wed, 11 Jan 2023 15:55:26 -0800 Message-Id: <20230111235531.3353815-5-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> References: <20230111235531.3353815-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH dii-client 4/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Paulo Zanoni Meteorlake has separate Media and render gt, it is necessary to process the interrupts for the gt separately. As part of it make sure IRQ reset and postinstall also work on Media gt. Signed-off-by: Paulo Zanoni Signed-off-by: Tvrtko Ursulin Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 54ea28cf8a1a..26d176ec4a66 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3170,14 +3170,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) { struct intel_gt *gt = to_gt(dev_priv); struct intel_uncore *uncore = gt->uncore; + unsigned int i; dg1_master_intr_disable(dev_priv->uncore.regs); - gen11_gt_irq_reset(gt); - gen11_display_irq_reset(dev_priv); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_reset(gt); - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); - GEN3_IRQ_RESET(uncore, GEN8_PCU_); + uncore = gt->uncore; + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); + GEN3_IRQ_RESET(uncore, GEN8_PCU_); + } + + gen11_display_irq_reset(dev_priv); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -3837,13 +3842,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) { - struct intel_gt *gt = to_gt(dev_priv); - struct intel_uncore *uncore = gt->uncore; u32 gu_misc_masked = GEN11_GU_MISC_GSE; + struct intel_gt *gt; + unsigned int i; - gen11_gt_irq_postinstall(gt); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_postinstall(gt); - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, + gu_misc_masked); + } if (HAS_DISPLAY(dev_priv)) { icp_irq_postinstall(dev_priv); @@ -3852,8 +3860,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) GEN11_DISPLAY_IRQ_ENABLE); } - dg1_master_intr_enable(uncore->regs); - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); } static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)