From patchwork Fri Jan 13 04:36:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Murthy, Arun R" X-Patchwork-Id: 13099752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 69885C54EBD for ; Fri, 13 Jan 2023 04:42:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F5B910E98B; Fri, 13 Jan 2023 04:42:34 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id AB8F510E986; Fri, 13 Jan 2023 04:42:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673584947; x=1705120947; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m0nEypF832E5Aa60hAqo51Felu0owHclhsv/xdyXnbs=; b=HgViJv7XCHukz37KbZXzLHCq7BazS/Y103pyb4WrdyltSimadZ0yiEhL 8MXlhQU2hhdgVSqYHHSaNWGq5+TG93i6QOw4V6KtXpFBgj4tysTzLcBMH 05vpzKHhrX4PriCzaKHwyIvieQyFxCsYqkbsAb6MysWMhtPCTGR5XOvZm tDVKyomMK0e6Qw+H8fLpyYgvklXcwyEMIC/N7C1MnU7lJn9oe842nYbs1 1gWnIr5fX8I5yfYpMbNpJ4lwnSYp8Rixh87M8lpvvMO4X+VS0pc7ljvNH AmBtQXyDAMArG5tioTwireARfbQ0bszveCQ350scJd9nwUJMAnOma2rbN w==; X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="325969974" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="325969974" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 20:42:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="608043043" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="608043043" Received: from srr4-3-linux-106-armuthy.iind.intel.com ([10.190.238.56]) by orsmga003.jf.intel.com with ESMTP; 12 Jan 2023 20:42:25 -0800 From: Arun R Murthy To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, jani.nikula@intel.com Date: Fri, 13 Jan 2023 10:06:53 +0530 Message-Id: <20230113043653.795183-2-arun.r.murthy@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230113043653.795183-1-arun.r.murthy@intel.com> References: <20230113043653.795183-1-arun.r.murthy@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] i915/display/dp: SDP CRC16 for 128b132b link layer X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Enable SDP error detection configuration, this will set CRC16 in 128b/132b link layer. For DISPLAY13 a hardware bit31 in register VIDEO_DIP_CTL is added to enable/disable SDP CRC applicable for DP2.0 only, but the default value of this bit will enable CRC16 in 128b/132b hence skipping this write. Corrective actions on SDP corruption is yet to be defined. Signed-off-by: Arun R Murthy --- drivers/gpu/drm/i915/display/intel_dp.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 30c55f980014..6096825a27ca 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -133,6 +133,7 @@ static void intel_dp_set_default_sink_rates(struct intel_dp *intel_dp) /* update sink rates from dpcd */ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); static const int dp_rates[] = { 162000, 270000, 540000, 810000 }; @@ -196,6 +197,18 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) intel_dp->sink_rates[i++] = 1350000; if (uhbr_rates & DP_UHBR20) intel_dp->sink_rates[i++] = 2000000; + + /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ + if (HAS_DP20(i915)) + drm_dp_dpcd_writeb(&intel_dp->aux, + DP_SDP_ERROR_DETECTION, + DP_SDP_CRC16_128B132B_EN); + /* + * VIDEO_DIP_CTL register bit 31 should be set to '0' to not + * disable SDP CRC. This is applicable for DISPLAY 13. Default + * value of bit 31 is '0' hence discarging the write + */ + /* TODO: Corrective actions on SDP corruption yet to be defined */ } intel_dp->num_sink_rates = i; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8b2cf980f323..77e265f59978 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2674,6 +2674,7 @@ #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) #define VIDEO_DIP_FREQ_MASK (3 << 16) /* HSW and later: */ +#define VIDEO_DISABLE_SDP_CRC (1 << 31) #define VIDEO_DIP_ENABLE_DRM_GLK (1 << 28) #define PSR_VSC_BIT_7_SET (1 << 27) #define VSC_SELECT_MASK (0x3 << 25)