| Message ID | 20230222073507.788705-4-radhakrishna.sripada@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Misc Meteorlake patches | expand |
On Tue, Feb 21, 2023 at 11:35:01PM -0800, Radhakrishna Sripada wrote: >Irq reset and post install are to be made multi-gt aware for the >interrupts to work for the media tile on Meteorlake. Iterate through >all the gts to process irq reset for each gt. > >Based on original version by Paulo and Tvrtko add a blank line here so the sentence above is not part of the commit trailers. >Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> >Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> >--- > drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++---------- > 1 file changed, 18 insertions(+), 10 deletions(-) > >diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >index b024a3a7ca19..be1212a5f4c5 100644 >--- a/drivers/gpu/drm/i915/i915_irq.c >+++ b/drivers/gpu/drm/i915/i915_irq.c >@@ -2761,14 +2761,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) > { > struct intel_gt *gt = to_gt(dev_priv); > struct intel_uncore *uncore = gt->uncore; probably better to remove these 2, so it's explicit what we are doing on a gt level and what we are doing on a device/root-gt level. struct intel_gt *gt; >+ unsigned int i; > > dg1_master_intr_disable(dev_priv->uncore.regs); > >- gen11_gt_irq_reset(gt); >- gen11_display_irq_reset(dev_priv); >+ for_each_gt(gt, dev_priv, i) { >+ gen11_gt_irq_reset(gt); ok > >- GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); >- GEN3_IRQ_RESET(uncore, GEN8_PCU_); >+ uncore = gt->uncore; remove this line >+ GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); >+ GEN3_IRQ_RESET(uncore, GEN8_PCU_); >+ } s/uncore/gt->uncore/ >+ >+ gen11_display_irq_reset(dev_priv); > } > > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, >@@ -3422,13 +3427,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) > > static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) > { >- struct intel_gt *gt = to_gt(dev_priv); >- struct intel_uncore *uncore = gt->uncore; > u32 gu_misc_masked = GEN11_GU_MISC_GSE; >+ struct intel_gt *gt; >+ unsigned int i; > >- gen11_gt_irq_postinstall(gt); >+ for_each_gt(gt, dev_priv, i) { >+ gen11_gt_irq_postinstall(gt); > >- GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); >+ GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, >+ gu_misc_masked); >+ } yep, the postinstall matches the logic I mentioned above. with the changes above, Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> thanks Lucas De Marchi > > if (HAS_DISPLAY(dev_priv)) { > icp_irq_postinstall(dev_priv); >@@ -3437,8 +3445,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) > GEN11_DISPLAY_IRQ_ENABLE); > } > >- dg1_master_intr_enable(uncore->regs); >- intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); >+ dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); >+ intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); > } > > static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv) >-- >2.34.1 >
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b024a3a7ca19..be1212a5f4c5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2761,14 +2761,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) { struct intel_gt *gt = to_gt(dev_priv); struct intel_uncore *uncore = gt->uncore; + unsigned int i; dg1_master_intr_disable(dev_priv->uncore.regs); - gen11_gt_irq_reset(gt); - gen11_display_irq_reset(dev_priv); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_reset(gt); - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); - GEN3_IRQ_RESET(uncore, GEN8_PCU_); + uncore = gt->uncore; + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); + GEN3_IRQ_RESET(uncore, GEN8_PCU_); + } + + gen11_display_irq_reset(dev_priv); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -3422,13 +3427,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) { - struct intel_gt *gt = to_gt(dev_priv); - struct intel_uncore *uncore = gt->uncore; u32 gu_misc_masked = GEN11_GU_MISC_GSE; + struct intel_gt *gt; + unsigned int i; - gen11_gt_irq_postinstall(gt); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_postinstall(gt); - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, + gu_misc_masked); + } if (HAS_DISPLAY(dev_priv)) { icp_irq_postinstall(dev_priv); @@ -3437,8 +3445,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) GEN11_DISPLAY_IRQ_ENABLE); } - dg1_master_intr_enable(uncore->regs); - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); } static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
Irq reset and post install are to be made multi-gt aware for the interrupts to work for the media tile on Meteorlake. Iterate through all the gts to process irq reset for each gt. Based on original version by Paulo and Tvrtko Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-)