From patchwork Wed Feb 22 07:35:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sripada, Radhakrishna" X-Patchwork-Id: 13148785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09D10C64EC4 for ; Wed, 22 Feb 2023 07:36:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7118A10E431; Wed, 22 Feb 2023 07:36:15 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEE8C10E3EB for ; Wed, 22 Feb 2023 07:35:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677051351; x=1708587351; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=+Q2f+dQDuYlsuF1giKzfCpsqejrZNQ04u5VkdQYZNYw=; b=HqxgyHjOrWC+YbpMCpFC8FSAywX1nNfyvKqQpMwkh8ejXsSTPGX2Q5fH 8vJuWa8GyCNAwqyP2b8DNrRiYUKfCbSeLKh0ET68NGAwUzviC9AwGHziZ M6oiONOzlhU0AVujg08NTOw/l5vOoY8IIwneIbmAzhSvUVuKqrB3U8EUA 1VeC2s/JM751lGHlaI9xjQERE60JVXe6mC/eJPRn7ysOXd2gAPf/k69by ptSzucWB/j7eN/Qw0S+i0WgPREJ93EdL0v10e8WNpasUpzfHcSjtrBP2Q pyRodSFjCanxyoNi1aq/EP+xGsB9ZfS5XEceZxkmcEyNEGGUerJbvBUsJ w==; X-IronPort-AV: E=McAfee;i="6500,9779,10628"; a="397544104" X-IronPort-AV: E=Sophos;i="5.97,318,1669104000"; d="scan'208";a="397544104" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2023 23:35:50 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10628"; a="795811229" X-IronPort-AV: E=Sophos;i="5.97,318,1669104000"; d="scan'208";a="795811229" Received: from invictus.jf.intel.com ([10.165.21.134]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Feb 2023 23:35:50 -0800 From: Radhakrishna Sripada To: intel-gfx@lists.freedesktop.org Date: Tue, 21 Feb 2023 23:35:01 -0800 Message-Id: <20230222073507.788705-4-radhakrishna.sripada@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230222073507.788705-1-radhakrishna.sripada@intel.com> References: <20230222073507.788705-1-radhakrishna.sripada@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 3/9] drm/i915/mtl: make IRQ reset and postinstall multi-gt aware X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Irq reset and post install are to be made multi-gt aware for the interrupts to work for the media tile on Meteorlake. Iterate through all the gts to process irq reset for each gt. Based on original version by Paulo and Tvrtko Cc: Paulo Zanoni Cc: Tvrtko Ursulin Signed-off-by: Radhakrishna Sripada --- drivers/gpu/drm/i915/i915_irq.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b024a3a7ca19..be1212a5f4c5 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2761,14 +2761,19 @@ static void dg1_irq_reset(struct drm_i915_private *dev_priv) { struct intel_gt *gt = to_gt(dev_priv); struct intel_uncore *uncore = gt->uncore; + unsigned int i; dg1_master_intr_disable(dev_priv->uncore.regs); - gen11_gt_irq_reset(gt); - gen11_display_irq_reset(dev_priv); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_reset(gt); - GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); - GEN3_IRQ_RESET(uncore, GEN8_PCU_); + uncore = gt->uncore; + GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_); + GEN3_IRQ_RESET(uncore, GEN8_PCU_); + } + + gen11_display_irq_reset(dev_priv); } void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, @@ -3422,13 +3427,16 @@ static void gen11_irq_postinstall(struct drm_i915_private *dev_priv) static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) { - struct intel_gt *gt = to_gt(dev_priv); - struct intel_uncore *uncore = gt->uncore; u32 gu_misc_masked = GEN11_GU_MISC_GSE; + struct intel_gt *gt; + unsigned int i; - gen11_gt_irq_postinstall(gt); + for_each_gt(gt, dev_priv, i) { + gen11_gt_irq_postinstall(gt); - GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked); + GEN3_IRQ_INIT(gt->uncore, GEN11_GU_MISC_, ~gu_misc_masked, + gu_misc_masked); + } if (HAS_DISPLAY(dev_priv)) { icp_irq_postinstall(dev_priv); @@ -3437,8 +3445,8 @@ static void dg1_irq_postinstall(struct drm_i915_private *dev_priv) GEN11_DISPLAY_IRQ_ENABLE); } - dg1_master_intr_enable(uncore->regs); - intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR); + dg1_master_intr_enable(to_gt(dev_priv)->uncore->regs); + intel_uncore_posting_read(to_gt(dev_priv)->uncore, DG1_MSTR_TILE_INTR); } static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)