| Message ID | 20230307032238.300674-1-gustavo.sousa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/xelp: Implement Wa_1606376872 | expand |
On Tue, Mar 07, 2023 at 12:22:38AM -0300, Gustavo Sousa wrote: > Wa_1606376872 applies to all Xe_LP IPs. "...except DG1" Aside from that, Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 08d76aa06974..4aecb5a7b631 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -478,6 +478,9 @@ > #define HDC_FORCE_NON_COHERENT (1 << 4) > #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) > > +#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) > +#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) > + > #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) > > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index 32aa1647721a..8092f289c492 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -743,9 +743,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, > FF_MODE2_GS_TIMER_224, > 0, false); > > - if (!IS_DG1(i915)) > + if (!IS_DG1(i915)) { > /* Wa_1806527549 */ > wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); > + > + /* Wa_1606376872 */ > + wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); > + } > } > > static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, > -- > 2.39.2 >
On Tue, Mar 07, 2023 at 12:12:46PM -0800, Matt Roper wrote: > On Tue, Mar 07, 2023 at 12:22:38AM -0300, Gustavo Sousa wrote: > > Wa_1606376872 applies to all Xe_LP IPs. > > "...except DG1" Oh, okay. I thought there was distinction between Xe_LP and Xe_LP+. > > Aside from that, > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Thanks for the review, Matt! Should I send a v2 or can the amend suggested above be done while applying? -- Gustavo Sousa > > > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++++- > > 2 files changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 08d76aa06974..4aecb5a7b631 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -478,6 +478,9 @@ > > #define HDC_FORCE_NON_COHERENT (1 << 4) > > #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) > > > > +#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) > > +#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) > > + > > #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) > > > > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index 32aa1647721a..8092f289c492 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -743,9 +743,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, > > FF_MODE2_GS_TIMER_224, > > 0, false); > > > > - if (!IS_DG1(i915)) > > + if (!IS_DG1(i915)) { > > /* Wa_1806527549 */ > > wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); > > + > > + /* Wa_1606376872 */ > > + wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); > > + } > > } > > > > static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, > > -- > > 2.39.2 > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation
On Tue, Mar 07, 2023 at 05:23:37PM -0300, Gustavo Sousa wrote: > On Tue, Mar 07, 2023 at 12:12:46PM -0800, Matt Roper wrote: > > On Tue, Mar 07, 2023 at 12:22:38AM -0300, Gustavo Sousa wrote: > > > Wa_1606376872 applies to all Xe_LP IPs. > > > > "...except DG1" > > Oh, okay. I thought there was distinction between Xe_LP and Xe_LP+. I think technically DG1 is considered "Xe_LP+" in some marketing material, but that's not a term we've ever used in our drivers so I don't think most people will be aware of it. Even "Xe_LP" has only been used once or twice in i915; generally we've just continued to refer to all of these older TGL/RKL/ADL/DG1 platforms as "gen12" since that name was already grandfathered in before the Xe branding was announced. Going back and trying to rename everything in i915 at this point would cause too much thrash (although when working on the Xe KMD where we don't have years of ancient history to deal with we should avoid the "gen" terminology from the start). > > > > > Aside from that, > > > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com> > > Thanks for the review, Matt! Should I send a v2 or can the amend suggested above > be done while applying? It can be done while applying. It looks like CI already came back clean, so I'll take care of that in a little bit. Matt > > -- > Gustavo Sousa > > > > > > > > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > > > --- > > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++++- > > > 2 files changed, 8 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > index 08d76aa06974..4aecb5a7b631 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > > @@ -478,6 +478,9 @@ > > > #define HDC_FORCE_NON_COHERENT (1 << 4) > > > #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) > > > > > > +#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) > > > +#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) > > > + > > > #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) > > > > > > #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) > > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > index 32aa1647721a..8092f289c492 100644 > > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > > @@ -743,9 +743,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, > > > FF_MODE2_GS_TIMER_224, > > > 0, false); > > > > > > - if (!IS_DG1(i915)) > > > + if (!IS_DG1(i915)) { > > > /* Wa_1806527549 */ > > > wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); > > > + > > > + /* Wa_1606376872 */ > > > + wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); > > > + } > > > } > > > > > > static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine, > > > -- > > > 2.39.2 > > > > > > > -- > > Matt Roper > > Graphics Software Engineer > > Linux GPU Platform Enablement > > Intel Corporation
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index 08d76aa06974..4aecb5a7b631 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -478,6 +478,9 @@ #define HDC_FORCE_NON_COHERENT (1 << 4) #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) +#define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) +#define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) + #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 32aa1647721a..8092f289c492 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -743,9 +743,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, FF_MODE2_GS_TIMER_224, 0, false); - if (!IS_DG1(i915)) + if (!IS_DG1(i915)) { /* Wa_1806527549 */ wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); + + /* Wa_1606376872 */ + wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); + } } static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,
Wa_1606376872 applies to all Xe_LP IPs. Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 +++++- 2 files changed, 8 insertions(+), 1 deletion(-)