diff mbox series

[v5,02/12] drm/i915/mtl: Synchronize i915/BIOS on C6 enabling

Message ID 20230316000932.2525744-3-umesh.nerlige.ramappa@intel.com (mailing list archive)
State New, archived
Headers show
Series Add OAM support for MTL | expand

Commit Message

Umesh Nerlige Ramappa March 16, 2023, 12:09 a.m. UTC 
From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

If BIOS enables/disables C6, i915 should do the same. Also, retain
this value across driver reloads. This is needed only for MTL as
of now due to an existing bug in OA which needs C6 disabled for
it to function. BIOS behavior is also different across platforms
in terms of how C6 is enabled.

Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_rc6.c       | 28 +++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_rc6.h       |  2 ++
 drivers/gpu/drm/i915/gt/intel_rc6_types.h |  2 ++
 3 files changed, 32 insertions(+)

Comments

Umesh Nerlige Ramappa March 16, 2023, 4:06 p.m. UTC | #1 
On Wed, Mar 15, 2023 at 05:09:22PM -0700, Umesh Nerlige Ramappa wrote:
>From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>
>If BIOS enables/disables C6, i915 should do the same. Also, retain
>this value across driver reloads. This is needed only for MTL as
>of now due to an existing bug in OA which needs C6 disabled for
>it to function. BIOS behavior is also different across platforms
>in terms of how C6 is enabled.
>
>Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_rc6.c       | 28 +++++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_rc6.h       |  2 ++
> drivers/gpu/drm/i915/gt/intel_rc6_types.h |  2 ++
> 3 files changed, 32 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
>index 5c91622dfca4..f760586f9f46 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>@@ -420,6 +420,21 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
> 	    GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
> }
>
>+bool intel_check_bios_c6_setup(struct intel_rc6 *rc6)
>+{
>+	if (!rc6->bios_state_captured) {
>+		struct intel_uncore *uncore = rc6_to_uncore(rc6);
>+		intel_wakeref_t wakeref;
>+
>+		with_intel_runtime_pm(uncore->rpm, wakeref)
>+			rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);
>+
>+		rc6->bios_state_captured = true;
>+	}
>+
>+	return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK;
>+}
>+
> static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
> {
> 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
>@@ -486,6 +501,7 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
> static bool rc6_supported(struct intel_rc6 *rc6)
> {
> 	struct drm_i915_private *i915 = rc6_to_i915(rc6);
>+	struct intel_gt *gt = rc6_to_gt(rc6);
>
> 	if (!HAS_RC6(i915))
> 		return false;
>@@ -502,6 +518,13 @@ static bool rc6_supported(struct intel_rc6 *rc6)
> 		return false;
> 	}
>
>+	if (IS_METEORLAKE(gt->i915) &&
>+	    !intel_check_bios_c6_setup(rc6)) {
>+		drm_notice(&i915->drm,
>+			   "C6 disabled by BIOS\n");
>+		return false;
>+	}
>+
> 	return true;
> }
>
>@@ -699,9 +722,14 @@ void intel_rc6_disable(struct intel_rc6 *rc6)
> void intel_rc6_fini(struct intel_rc6 *rc6)
> {
> 	struct drm_i915_gem_object *pctx;
>+	struct intel_uncore *uncore = rc6_to_uncore(rc6);
>
> 	intel_rc6_disable(rc6);
>
>+	/* We want the BIOS C6 state preserved across loads for MTL */
>+	if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
>+		set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
>+

Assuming bios_state_captured will be false on driver load because gt is 
zalloc-ed. With that, this lgtm

Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>

Regards,
Umesh
> 	pctx = fetch_and_zero(&rc6->pctx);
> 	if (pctx)
> 		i915_gem_object_put(pctx);
>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h
>index 456fa668a276..e137c2c397c2 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rc6.h
>+++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
>@@ -27,4 +27,6 @@ u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
> void intel_rc6_print_residency(struct seq_file *m, const char *title,
> 			       enum intel_rc6_res_type id);
>
>+bool intel_check_bios_c6_setup(struct intel_rc6 *rc6);
>+
> #endif /* INTEL_RC6_H */
>diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
>index fa23c4dce00b..cd4587098162 100644
>--- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
>+++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
>@@ -29,6 +29,7 @@ struct intel_rc6 {
> 	u64 cur_residency[INTEL_RC6_RES_MAX];
>
> 	u32 ctl_enable;
>+	u32 bios_rc_state;
>
> 	struct drm_i915_gem_object *pctx;
>
>@@ -36,6 +37,7 @@ struct intel_rc6 {
> 	bool enabled : 1;
> 	bool manual : 1;
> 	bool wakeref : 1;
>+	bool bios_state_captured : 1;
> };
>
> #endif /* INTEL_RC6_TYPES_H */
>-- 
>2.36.1
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 5c91622dfca4..f760586f9f46 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -420,6 +420,21 @@  static void vlv_rc6_enable(struct intel_rc6 *rc6)
 	    GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
 }
 
+bool intel_check_bios_c6_setup(struct intel_rc6 *rc6)
+{
+	if (!rc6->bios_state_captured) {
+		struct intel_uncore *uncore = rc6_to_uncore(rc6);
+		intel_wakeref_t wakeref;
+
+		with_intel_runtime_pm(uncore->rpm, wakeref)
+			rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);
+
+		rc6->bios_state_captured = true;
+	}
+
+	return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK;
+}
+
 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
 {
 	struct intel_uncore *uncore = rc6_to_uncore(rc6);
@@ -486,6 +501,7 @@  static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
 static bool rc6_supported(struct intel_rc6 *rc6)
 {
 	struct drm_i915_private *i915 = rc6_to_i915(rc6);
+	struct intel_gt *gt = rc6_to_gt(rc6);
 
 	if (!HAS_RC6(i915))
 		return false;
@@ -502,6 +518,13 @@  static bool rc6_supported(struct intel_rc6 *rc6)
 		return false;
 	}
 
+	if (IS_METEORLAKE(gt->i915) &&
+	    !intel_check_bios_c6_setup(rc6)) {
+		drm_notice(&i915->drm,
+			   "C6 disabled by BIOS\n");
+		return false;
+	}
+
 	return true;
 }
 
@@ -699,9 +722,14 @@  void intel_rc6_disable(struct intel_rc6 *rc6)
 void intel_rc6_fini(struct intel_rc6 *rc6)
 {
 	struct drm_i915_gem_object *pctx;
+	struct intel_uncore *uncore = rc6_to_uncore(rc6);
 
 	intel_rc6_disable(rc6);
 
+	/* We want the BIOS C6 state preserved across loads for MTL */
+	if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
+		set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
+
 	pctx = fetch_and_zero(&rc6->pctx);
 	if (pctx)
 		i915_gem_object_put(pctx);
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.h b/drivers/gpu/drm/i915/gt/intel_rc6.h
index 456fa668a276..e137c2c397c2 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.h
@@ -27,4 +27,6 @@  u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id);
 void intel_rc6_print_residency(struct seq_file *m, const char *title,
 			       enum intel_rc6_res_type id);
 
+bool intel_check_bios_c6_setup(struct intel_rc6 *rc6);
+
 #endif /* INTEL_RC6_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6_types.h b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
index fa23c4dce00b..cd4587098162 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_rc6_types.h
@@ -29,6 +29,7 @@  struct intel_rc6 {
 	u64 cur_residency[INTEL_RC6_RES_MAX];
 
 	u32 ctl_enable;
+	u32 bios_rc_state;
 
 	struct drm_i915_gem_object *pctx;
 
@@ -36,6 +37,7 @@  struct intel_rc6 {
 	bool enabled : 1;
 	bool manual : 1;
 	bool wakeref : 1;
+	bool bios_state_captured : 1;
 };
 
 #endif /* INTEL_RC6_TYPES_H */