From patchwork Thu Mar 16 11:13:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kahola X-Patchwork-Id: 13177412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 28801C7618A for ; Thu, 16 Mar 2023 11:19:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4784B10ECAB; Thu, 16 Mar 2023 11:19:16 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B9B310ECB2 for ; Thu, 16 Mar 2023 11:19:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678965550; x=1710501550; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5/ITx5fUNesJv2rQykD0ZZVaft/50SAUhC9ZIYYkh8A=; b=blvUlbejz1Gfvr1S2aY/8hS9+EyZq5WvsPsy5cEq3QCwbjxZvVgv6AVZ ec8L/xwpqbOvamnqB/DJNIstsXyCQ2Eqd6hIMQq58C74lN2nUjK/d2bVW mLRalbfy5mDc39fH1YyCShA5rpGFSBu5BFROgWcQWf4lYL7FmLaoTtXXQ P8CX/nEyWKJBGj9xntPV61jeqJYL27eFI6FAHpaVImK/6lq0QJ/VAUEV3 F4kEsrR9VMMIrAhYXsbPkldyBICU3ZVa3eodTTEoY9/HQs+rdQdaaKRpf 0i8y+U7XjQHe7vlqc47PA7GgYsAYqSqAOT6YgmEA7bxXzt1lgX+Jf+6Dn A==; X-IronPort-AV: E=McAfee;i="6500,9779,10650"; a="339485891" X-IronPort-AV: E=Sophos;i="5.98,265,1673942400"; d="scan'208";a="339485891" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2023 04:19:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10650"; a="744083219" X-IronPort-AV: E=Sophos;i="5.98,265,1673942400"; d="scan'208";a="744083219" Received: from sorvi2.fi.intel.com ([10.237.72.194]) by fmsmga008.fm.intel.com with ESMTP; 16 Mar 2023 04:19:08 -0700 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Mar 2023 13:13:23 +0200 Message-Id: <20230316111335.66915-11-mika.kahola@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230316111335.66915-1-mika.kahola@intel.com> References: <20230316111335.66915-1-mika.kahola@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 10/22] drm/i915/mtl: Dump C20 pll hw state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" As we already do with C10 chip, let's dump the pll hw state for C20 as well. Signed-off-by: Mika Kahola --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 20 ++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_cx0_phy.h | 2 ++ drivers/gpu/drm/i915/display/intel_ddi.c | 1 + 3 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index bfb264ea154a..bc6913a7444a 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -1874,6 +1874,26 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, } } +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, + const struct intel_c20pll_state *hw_state) +{ + int i; + + drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); + drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", + hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); + drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", + hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); + + if (intel_c20_use_mplla(hw_state->clock)) { + for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) + drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); + } else { + for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) + drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); + } +} + static u8 intel_c20_get_dp_rate(u32 clock) { switch (clock) { diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index cf603080ce3d..0b46b2ad48a9 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -37,6 +37,8 @@ void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, struct intel_c20pll_state *pll_state); void intel_c10mpllb_dump_hw_state(struct drm_i915_private *dev_priv, const struct intel_c10mpllb_state *hw_state); +void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, + const struct intel_c20pll_state *hw_state); int intel_c10mpllb_calc_port_clock(struct intel_encoder *encoder, const struct intel_c10mpllb_state *pll_state); void intel_c10mpllb_state_verify(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 14b8dcee1c0c..d94add6e322d 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3521,6 +3521,7 @@ static void mtl_ddi_get_config(struct intel_encoder *encoder, intel_c10mpllb_dump_hw_state(i915, &crtc_state->cx0pll_state.c10mpllb_state); } else { intel_c20pll_readout_hw_state(encoder, &crtc_state->cx0pll_state.c20pll_state); + intel_c20pll_dump_hw_state(i915, &crtc_state->cx0pll_state.c20pll_state); } crtc_state->port_clock = intel_c10mpllb_calc_port_clock(encoder, &crtc_state->cx0pll_state.c10mpllb_state);