From patchwork Thu Mar 16 11:13:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kahola, Mika" X-Patchwork-Id: 13177423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 60C2BC6FD19 for ; Thu, 16 Mar 2023 11:19:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DDC4710ECCD; Thu, 16 Mar 2023 11:19:29 +0000 (UTC) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 24F3710ECBE for ; Thu, 16 Mar 2023 11:19:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1678965568; x=1710501568; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IwPYV4oAA8CfG3FNxbtEZqr0ogXh0Y3BWHYn/P8yJcI=; b=ORY/nS1dcVOv8/XlCcx0swxRvFzrZXhONYB3A5Nt9w18k3iS46+PvU76 ZyTIoOgNHTvJLYIBAkcsxLbZxpgMYSlY8OiNZ8fAo3pYdm7vWSmhpKcOq J5nTwlmG9E+5MlpAm6PFtwDHgOXLnErTR2WTkNmlEqdJq03w2Cc1melAY qf0SboQXFTfITuJMzhakgu6yRYZ+2zLeugD2rm9lL3DgfrUWfG9jSTxfT LrtxFOxdTlnhH3g0/f9nhQ4nZECtTU/9yJAVJuVY34duQL+nigspgnVEP x8CrfXJqRcebqci4ZGTxelhgsQ8GD4Hrsr6bQE7KPgSpGIEO1ZqQU6jda Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10650"; a="339486016" X-IronPort-AV: E=Sophos;i="5.98,265,1673942400"; d="scan'208";a="339486016" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2023 04:19:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10650"; a="744083329" X-IronPort-AV: E=Sophos;i="5.98,265,1673942400"; d="scan'208";a="744083329" Received: from sorvi2.fi.intel.com ([10.237.72.194]) by fmsmga008.fm.intel.com with ESMTP; 16 Mar 2023 04:19:25 -0700 From: Mika Kahola To: intel-gfx@lists.freedesktop.org Date: Thu, 16 Mar 2023 13:13:35 +0200 Message-Id: <20230316111335.66915-23-mika.kahola@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230316111335.66915-1-mika.kahola@intel.com> References: <20230316111335.66915-1-mika.kahola@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v5 22/22] drm/i915/mtl: Pin assignment for TypeC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Matt Roper Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Anusha Srivatsa Unlike previous platforms that used PORT_TX_DFLEXDPSP for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1 from which the max_lanes has to be calculated. Bspec: 50235, 65380 Cc: Mika Kahola Cc: Imre Deak Cc: Matt Roper Signed-off-by: Anusha Srivatsa Signed-off-by: Jose Roberto de Souza --- drivers/gpu/drm/i915/display/intel_tc.c | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index 5756daac91d9..694d74088980 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -15,6 +15,10 @@ #include "intel_mg_phy_regs.h" #include "intel_tc.h" +#define DP_PIN_ASSIGNMENT_C 0x3 +#define DP_PIN_ASSIGNMENT_D 0x4 +#define DP_PIN_ASSIGNMENT_E 0x5 + static const char *tc_port_mode_name(enum tc_port_mode mode) { static const char * const names[] = { @@ -147,6 +151,29 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) DP_PIN_ASSIGNMENT_SHIFT(dig_port->tc_phy_fia_idx); } +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + intel_wakeref_t wakeref; + u32 pin_mask; + + assert_tc_cold_blocked(dig_port); + + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); + + switch(pin_mask) { + default: + MISSING_CASE(pin_mask); + fallthrough; + case DP_PIN_ASSIGNMENT_D: + return 2; + case DP_PIN_ASSIGNMENT_C: + case DP_PIN_ASSIGNMENT_E: + return 4; + } +} + int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -156,6 +183,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) if (dig_port->tc_mode != TC_PORT_DP_ALT) return 4; + if (DISPLAY_VER(i915) >= 14) + return mtl_tc_port_get_pin_assignment_mask(dig_port); + assert_tc_cold_blocked(dig_port); lane_mask = 0;