From patchwork Wed Apr 5 06:00:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Riana Tauro X-Patchwork-Id: 13201158 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9A42AC7619A for ; Wed, 5 Apr 2023 06:00:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 38EB610E0EC; Wed, 5 Apr 2023 06:00:49 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id B404B10E0EC for ; Wed, 5 Apr 2023 06:00:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1680674447; x=1712210447; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=EOmt1uGdJMj34XxyT7egA4tBwOXEce1MgvbHLdNdYdc=; b=DtsXlCoxrN00fy3krgezbKmCMJA6m9shFoXgRIzk6D7GtLo3SShBiSJn 6OndkwP4RcAPRzifn0VsiolbvkrkkIsRWkhuVHFFEKR9QjofiNfw5edpM u/nCD83hPSTd92ZoI7Gk4/ZbUf5altgkT4cADe9RGu3/ksgBiygXZA6GL P02BIxpcanwebbyNC17/L6vPPVYk5duDuHcQoKM5Lcx2vJJ8WgH/oQx5x BnwtwSeCryLhhOVQs7z+B4vAxIp/bUE02R8hYt9YhKyLXb/Sgb+2ETw/Z txHXYEq0znjJ390kNgxjQe7KMWuc0egNw7NT+jlZz/wjDeDAdFd99Y/y5 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10670"; a="326412494" X-IronPort-AV: E=Sophos;i="5.98,319,1673942400"; d="scan'208";a="326412494" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 23:00:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10670"; a="860849575" X-IronPort-AV: E=Sophos;i="5.98,319,1673942400"; d="scan'208";a="860849575" Received: from rtauro-desk.iind.intel.com ([10.190.239.41]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2023 23:00:41 -0700 From: Riana Tauro To: intel-gfx@lists.freedesktop.org Date: Wed, 5 Apr 2023 11:30:27 +0530 Message-Id: <20230405060029.3574262-3-riana.tauro@intel.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230405060029.3574262-1-riana.tauro@intel.com> References: <20230405060029.3574262-1-riana.tauro@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v8 2/4] drm/i915/hwmon: Add helper function to obtain energy values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add an interface to obtain hwmon energy values. The function returns per-gt energy if gt level energy is available else returns the package level energy if there is a single gt. This is used by selftests to verify power consumption v2 : use i915_hwmon prefix (Anshuman) v3 : re-use is_visible function of energy to remove redundant code (Anshuman) v4 : fix kernel-doc (Anshuman) add per-gt hwmon support (Ashutosh) v5 : add check to return package level energy only when there is a single gt and gt level energy is not available. (Ashutosh) Signed-off-by: Riana Tauro Reviewed-by: Anshuman Gupta Reviewed-by: Ashutosh Dixit --- drivers/gpu/drm/i915/i915_hwmon.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_hwmon.h | 3 +++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_hwmon.c b/drivers/gpu/drm/i915/i915_hwmon.c index 8e7dccc8d3a0..efc2ccaf64d1 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.c +++ b/drivers/gpu/drm/i915/i915_hwmon.c @@ -500,6 +500,34 @@ hwm_energy_read(struct hwm_drvdata *ddat, u32 attr, long *val) } } +/** + * i915_hwmon_get_energy - obtains energy value + * @gt: intel_gt structure + * @energy: pointer to store energy in uJ + * + * This function checks for the validity of the underlying energy + * hardware register and obtains per-gt level energy + * values. + * + * Return: 0 on success, -EOPNOTSUPP if register is invalid + */ +int +i915_hwmon_get_energy(struct intel_gt *gt, long *energy) +{ + struct i915_hwmon *hwmon = gt->i915->hwmon; + struct hwm_drvdata *ddat = &hwmon->ddat; + struct hwm_drvdata *ddat_gt = hwmon->ddat_gt + gt->info.id; + + if (hwm_energy_is_visible(ddat_gt, hwmon_energy_input)) + hwm_energy(ddat_gt, energy); + else if (!HAS_EXTRA_GT_LIST(gt->i915) && hwm_energy_is_visible(ddat, hwmon_energy_input)) + hwm_energy(ddat, energy); + else + return -EOPNOTSUPP; + + return 0; +} + static umode_t hwm_curr_is_visible(const struct hwm_drvdata *ddat, u32 attr) { diff --git a/drivers/gpu/drm/i915/i915_hwmon.h b/drivers/gpu/drm/i915/i915_hwmon.h index 7ca9cf2c34c9..1c38cfdbb7e9 100644 --- a/drivers/gpu/drm/i915/i915_hwmon.h +++ b/drivers/gpu/drm/i915/i915_hwmon.h @@ -8,13 +8,16 @@ #define __I915_HWMON_H__ struct drm_i915_private; +struct intel_gt; #if IS_REACHABLE(CONFIG_HWMON) void i915_hwmon_register(struct drm_i915_private *i915); void i915_hwmon_unregister(struct drm_i915_private *i915); +int i915_hwmon_get_energy(struct intel_gt *gt, long *energy); #else static inline void i915_hwmon_register(struct drm_i915_private *i915) { }; static inline void i915_hwmon_unregister(struct drm_i915_private *i915) { }; +static inline int i915_hwmon_get_energy(struct intel_gt *gt, long *energy) { return -EOPNOTSUPP; } #endif #endif /* __I915_HWMON_H__ */