| Message ID | 20230420124050.3617608-13-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/mtl: Add support for C20 phy | expand |
On Thu, Apr 20, 2023 at 03:40:49PM +0300, Mika Kahola wrote: > From: Anusha Srivatsa <anusha.srivatsa@intel.com> > > Unlike previous platforms that used PORT_TX_DFLEXDPSP > for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1 > from which the max_lanes has to be calculated. > > Bspec: 50235, 65380 > Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > Signed-off-by: Jose Roberto de Souza <jose.souza@intel.com> > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c > index b192265a3d78..4fca711a58bc 100644 > --- a/drivers/gpu/drm/i915/display/intel_tc.c > +++ b/drivers/gpu/drm/i915/display/intel_tc.c > @@ -16,6 +16,10 @@ > #include "intel_mg_phy_regs.h" > #include "intel_tc.h" > > +#define DP_PIN_ASSIGNMENT_C 0x3 > +#define DP_PIN_ASSIGNMENT_D 0x4 > +#define DP_PIN_ASSIGNMENT_E 0x5 > + > enum tc_port_mode { > TC_PORT_DISCONNECTED, > TC_PORT_TBT_ALT, > @@ -281,6 +285,27 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) > DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx); > } > > +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) > +{ > + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > + intel_wakeref_t wakeref; > + u32 pin_mask; > + > + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) > + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); > + > + switch (pin_mask) { > + default: > + MISSING_CASE(pin_mask); > + fallthrough; > + case DP_PIN_ASSIGNMENT_D: > + return 2; > + case DP_PIN_ASSIGNMENT_C: > + case DP_PIN_ASSIGNMENT_E: > + return 4; > + } > +} > + > int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) > { > struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); > @@ -294,6 +319,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) > > assert_tc_cold_blocked(tc); > > + if (DISPLAY_VER(i915) >= 14) > + return mtl_tc_port_get_pin_assignment_mask(dig_port); > + > lane_mask = 0; > with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) > lane_mask = intel_tc_port_get_lane_mask(dig_port); > -- > 2.34.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c index b192265a3d78..4fca711a58bc 100644 --- a/drivers/gpu/drm/i915/display/intel_tc.c +++ b/drivers/gpu/drm/i915/display/intel_tc.c @@ -16,6 +16,10 @@ #include "intel_mg_phy_regs.h" #include "intel_tc.h" +#define DP_PIN_ASSIGNMENT_C 0x3 +#define DP_PIN_ASSIGNMENT_D 0x4 +#define DP_PIN_ASSIGNMENT_E 0x5 + enum tc_port_mode { TC_PORT_DISCONNECTED, TC_PORT_TBT_ALT, @@ -281,6 +285,27 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx); } +static int mtl_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port) +{ + struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); + intel_wakeref_t wakeref; + u32 pin_mask; + + with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) + pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port); + + switch (pin_mask) { + default: + MISSING_CASE(pin_mask); + fallthrough; + case DP_PIN_ASSIGNMENT_D: + return 2; + case DP_PIN_ASSIGNMENT_C: + case DP_PIN_ASSIGNMENT_E: + return 4; + } +} + int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) { struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); @@ -294,6 +319,9 @@ int intel_tc_port_fia_max_lane_count(struct intel_digital_port *dig_port) assert_tc_cold_blocked(tc); + if (DISPLAY_VER(i915) >= 14) + return mtl_tc_port_get_pin_assignment_mask(dig_port); + lane_mask = 0; with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref) lane_mask = intel_tc_port_get_lane_mask(dig_port);