diff mbox series

[6/6] drm/i915/guc: Capture list clean up - 5

Message ID 20230426182407.4097589-1-John.C.Harrison@Intel.com (mailing list archive)
State New, archived
Headers show
Series None | expand

Commit Message

John Harrison April 26, 2023, 6:24 p.m. UTC 
From: John Harrison <John.C.Harrison@Intel.com>

Rename the 'default_' register list prefix to 'gen8_' as that is the
more accurate name.

Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Comments

Alan Previn April 26, 2023, 9:16 p.m. UTC | #1 
On Wed, 2023-04-26 at 11:24 -0700, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
> 
> Rename the 'default_' register list prefix to 'gen8_' as that is the
> more accurate name.
> 
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>

Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index c1a75a2d17f1e..729a8fcf20dda 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -141,13 +141,13 @@  static const struct __guc_mmio_reg_descr xe_lp_gsc_inst_regs[] = {
 };
 
 /* GEN8 - Global */
-static const struct __guc_mmio_reg_descr default_global_regs[] = {
+static const struct __guc_mmio_reg_descr gen8_global_regs[] = {
 	COMMON_BASE_GLOBAL,
 	COMMON_GEN8BASE_GLOBAL,
 	GEN8_GLOBAL,
 };
 
-static const struct __guc_mmio_reg_descr default_rc_class_regs[] = {
+static const struct __guc_mmio_reg_descr gen8_rc_class_regs[] = {
 	COMMON_BASE_HAS_EU,
 	COMMON_BASE_RENDER,
 };
@@ -172,11 +172,11 @@  static const struct __guc_mmio_reg_descr empty_regs_list[] = {
 	}
 
 /* List of lists */
-static const struct __guc_mmio_reg_descr_group default_lists[] = {
-	MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
-	MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
+static const struct __guc_mmio_reg_descr_group gen8_lists[] = {
+	MAKE_REGLIST(gen8_global_regs, PF, GLOBAL, 0),
+	MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_RENDER_CLASS),
 	MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_RENDER_CLASS),
-	MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
+	MAKE_REGLIST(gen8_rc_class_regs, PF, ENGINE_CLASS, GUC_COMPUTE_CLASS),
 	MAKE_REGLIST(gen8_rc_inst_regs, PF, ENGINE_INSTANCE, GUC_COMPUTE_CLASS),
 	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_VIDEO_CLASS),
 	MAKE_REGLIST(gen8_vd_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEO_CLASS),
@@ -366,7 +366,7 @@  guc_capture_get_device_reglist(struct intel_guc *guc)
 	if (GRAPHICS_VER(i915) >= 12)
 		lists = xe_lp_lists;
 	else
-		lists = default_lists;
+		lists = gen8_lists;
 
 	/*
 	 * For certain engine classes, there are slice and subslice