From patchwork Tue May 30 18:55:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 13260982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7C2D7C77B73 for ; Tue, 30 May 2023 18:54:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E2D1610E1AC; Tue, 30 May 2023 18:54:04 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 91C9810E1AC for ; Tue, 30 May 2023 18:54:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685472843; x=1717008843; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XiHUQg0QLR1vLaygEsTfm/v4cgGAKgEqQ4DbloWu8jA=; b=K/PJGa+L2J/lqiDWYCAjJBwCPlq3k2k2NjQDctoRAjixxn07k0XM32iR bv5HayIHNc1Pwvk9f94mbBgBsUqJdkgMhwDiB0WwcqNXY2B9KTDExPVvq uvCrgFmB6vHOEjSA0gHltZ7K7Z53gE4D9mttFrvK/t1bj2jE8WD3Thrd4 ZdyrlO5oj+8KKYkehO6PKA2r89Oh3b5peRYdIHJJ+CefeeRq7UJAnN3wO Dx15mIG4BqtHzsY6QZcG9lS0ZzZvadnm+2olrEz1AeScesOc2ZrPTCCte yCDK4OLt1FDbOXcQSAdReVNJu1PVSBKIavHYXtqEAkQSewZ3vNXINejAu A==; X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="418504046" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="418504046" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2023 11:54:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10726"; a="796381486" X-IronPort-AV: E=Sophos;i="6.00,205,1681196400"; d="scan'208";a="796381486" Received: from anushasr-simics.jf.intel.com ([10.165.21.205]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 May 2023 11:53:58 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Tue, 30 May 2023 11:55:27 -0700 Message-Id: <20230530185529.3378520-4-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230530185529.3378520-1-anusha.srivatsa@intel.com> References: <20230530185529.3378520-1-anusha.srivatsa@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/5] drm/i915/rplu: s/ADLP/ALDERLAKE_P in RPLU defines X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Follow consistent naming convention. Replace ADLP with ALDERLAKE_P Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 013678caaca8..4420de5ffe9c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3543,7 +3543,7 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) /* Wa_22011320316:adl-p[a0] */ if (IS_ALDERLAKE_P_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; - else if (IS_ADLP_RPLU(dev_priv)) + else if (IS_ALDERLAKE_P_RPLU(dev_priv)) dev_priv->display.cdclk.table = rplu_cdclk_table; else dev_priv->display.cdclk.table = adlp_cdclk_table; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 43414cdc137c..d400cecb318b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -583,7 +583,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) #define IS_ALDERLAKE_P_RPLP(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL) -#define IS_ADLP_RPLU(i915) \ +#define IS_ALDERLAKE_P_RPLU(i915) \ IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU) #define IS_HSW_EARLY_SDV(i915) (IS_HASWELL(i915) && \ (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)