| Message ID | 20230609002038.11516-1-shawn.c.lee@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4] drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4 | expand |
Merged. Thank you for the patch and review. --Radhakrishna(RK) Sripada > -----Original Message----- > From: Lee, Shawn C <shawn.c.lee@intel.com> > Sent: Thursday, June 8, 2023 5:21 PM > To: intel-gfx@lists.freedesktop.org > Cc: Lee, Shawn C <shawn.c.lee@intel.com>; Kahola, Mika > <mika.kahola@intel.com>; Taylor, Clinton A <clinton.a.taylor@intel.com>; > Sripada, Radhakrishna <radhakrishna.sripada@intel.com>; Shankar, Uma > <uma.shankar@intel.com> > Subject: [v4] drm/i915/mtl: Add new vswing table for C20 phy to support DP 1.4 > > Add vswing table to support DP 1.4 for C20 phy. > > v2: rename mtl_c10_trans > v3: add default_entry for mtl_c20_trans_dp14 > v4: rename mtl_cx0_trans_dp14 > > Bspec: 74104 > Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com> > Cc: Mika Kahola <mika.kahola@intel.com> > Cc: Clint Taylor <Clinton.A.Taylor@intel.com> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Cc: Uma Shankar <uma.shankar@intel.com> > Reviewed-by: Mika Kahola <mika.kahola@intel.com> > Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > --- > .../drm/i915/display/intel_ddi_buf_trans.c | 26 +++++++++++++++++-- > 1 file changed, 24 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index b7d20485bde5..8d2932d079cf 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1049,12 +1049,26 @@ static const union intel_ddi_buf_trans_entry > _mtl_c10_trans_dp14[] = { > { .snps = { 62, 0, 0 } }, /* preset 9 */ > }; > > -static const struct intel_ddi_buf_trans mtl_cx0_trans = { > +static const struct intel_ddi_buf_trans mtl_c10_trans_dp14 = { > .entries = _mtl_c10_trans_dp14, > .num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14), > .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1, > }; > > +/* DP1.4 */ > +static const union intel_ddi_buf_trans_entry _mtl_c20_trans_dp14[] = { > + { .snps = { 20, 0, 0 } }, /* preset 0 */ > + { .snps = { 24, 0, 4 } }, /* preset 1 */ > + { .snps = { 30, 0, 9 } }, /* preset 2 */ > + { .snps = { 34, 0, 14 } }, /* preset 3 */ > + { .snps = { 29, 0, 0 } }, /* preset 4 */ > + { .snps = { 34, 0, 5 } }, /* preset 5 */ > + { .snps = { 38, 0, 10 } }, /* preset 6 */ > + { .snps = { 36, 0, 0 } }, /* preset 7 */ > + { .snps = { 40, 0, 6 } }, /* preset 8 */ > + { .snps = { 48, 0, 0 } }, /* preset 9 */ > +}; > + > /* DP2.0 */ > static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = { > { .snps = { 48, 0, 0 } }, /* preset 0 */ > @@ -1090,6 +1104,12 @@ static const struct intel_ddi_buf_trans > mtl_c20_trans_hdmi = { > .hdmi_default_entry = 0, > }; > > +static const struct intel_ddi_buf_trans mtl_c20_trans_dp14 = { > + .entries = _mtl_c20_trans_dp14, > + .num_entries = ARRAY_SIZE(_mtl_c20_trans_dp14), > + .hdmi_default_entry = ARRAY_SIZE(_mtl_c20_trans_dp14) - 1, > +}; > + > static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = { > .entries = _mtl_c20_trans_uhbr, > .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr), > @@ -1678,8 +1698,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder > *encoder, > return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries); > else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && > !(intel_is_c10phy(i915, phy))) > return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries); > + else if (!intel_is_c10phy(i915, phy)) > + return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries); > else > - return intel_get_buf_trans(&mtl_cx0_trans, n_entries); > + return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries); > } > > void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > -- > 2.17.1
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index b7d20485bde5..8d2932d079cf 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1049,12 +1049,26 @@ static const union intel_ddi_buf_trans_entry _mtl_c10_trans_dp14[] = { { .snps = { 62, 0, 0 } }, /* preset 9 */ }; -static const struct intel_ddi_buf_trans mtl_cx0_trans = { +static const struct intel_ddi_buf_trans mtl_c10_trans_dp14 = { .entries = _mtl_c10_trans_dp14, .num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14), .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1, }; +/* DP1.4 */ +static const union intel_ddi_buf_trans_entry _mtl_c20_trans_dp14[] = { + { .snps = { 20, 0, 0 } }, /* preset 0 */ + { .snps = { 24, 0, 4 } }, /* preset 1 */ + { .snps = { 30, 0, 9 } }, /* preset 2 */ + { .snps = { 34, 0, 14 } }, /* preset 3 */ + { .snps = { 29, 0, 0 } }, /* preset 4 */ + { .snps = { 34, 0, 5 } }, /* preset 5 */ + { .snps = { 38, 0, 10 } }, /* preset 6 */ + { .snps = { 36, 0, 0 } }, /* preset 7 */ + { .snps = { 40, 0, 6 } }, /* preset 8 */ + { .snps = { 48, 0, 0 } }, /* preset 9 */ +}; + /* DP2.0 */ static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = { { .snps = { 48, 0, 0 } }, /* preset 0 */ @@ -1090,6 +1104,12 @@ static const struct intel_ddi_buf_trans mtl_c20_trans_hdmi = { .hdmi_default_entry = 0, }; +static const struct intel_ddi_buf_trans mtl_c20_trans_dp14 = { + .entries = _mtl_c20_trans_dp14, + .num_entries = ARRAY_SIZE(_mtl_c20_trans_dp14), + .hdmi_default_entry = ARRAY_SIZE(_mtl_c20_trans_dp14) - 1, +}; + static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = { .entries = _mtl_c20_trans_uhbr, .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr), @@ -1678,8 +1698,10 @@ mtl_get_cx0_buf_trans(struct intel_encoder *encoder, return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries); else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_is_c10phy(i915, phy))) return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries); + else if (!intel_is_c10phy(i915, phy)) + return intel_get_buf_trans(&mtl_c20_trans_dp14, n_entries); else - return intel_get_buf_trans(&mtl_cx0_trans, n_entries); + return intel_get_buf_trans(&mtl_c10_trans_dp14, n_entries); } void intel_ddi_buf_trans_init(struct intel_encoder *encoder)