| Message ID | 20230616013850.611281-1-umesh.nerlige.ramappa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915/perf: Determine context valid in OA reports | expand |
On Thu, 15 Jun 2023 18:38:50 -0700, Umesh Nerlige Ramappa wrote: > Hi Umesh, > When supporting OA for TGL, it was seen that the context valid bit in > the report ID was not defined, however revisiting the spec seems to have > this bit defined. The bit is used to determine if a context is valid on > a context switch and is essential to determine active and idle periods > for a context. Re-enable the context valid bit for gen12 platforms. A Bspec reference here would be nice if available. Otherwise this is: Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com> > > Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL") > Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> > --- > drivers/gpu/drm/i915/i915_perf.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 0a111b281578..b5491a382bfd 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -482,8 +482,7 @@ static void oa_report_id_clear(struct i915_perf_stream *stream, u32 *report) > static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report) > { > return !(oa_report_id(stream, report) & > - stream->perf->gen8_valid_ctx_bit) && > - GRAPHICS_VER(stream->perf->i915) <= 11; > + stream->perf->gen8_valid_ctx_bit); > } > > static u64 oa_timestamp(struct i915_perf_stream *stream, void *report) > @@ -5096,6 +5095,7 @@ static void i915_perf_init_info(struct drm_i915_private *i915) > perf->gen8_valid_ctx_bit = BIT(16); > break; > case 12: > + perf->gen8_valid_ctx_bit = BIT(16); > /* > * Calculate offset at runtime in oa_pin_context for gen12 and > * cache the value in perf->ctx_oactxctrl_offset. > -- > 2.36.1 >
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 0a111b281578..b5491a382bfd 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -482,8 +482,7 @@ static void oa_report_id_clear(struct i915_perf_stream *stream, u32 *report) static bool oa_report_ctx_invalid(struct i915_perf_stream *stream, void *report) { return !(oa_report_id(stream, report) & - stream->perf->gen8_valid_ctx_bit) && - GRAPHICS_VER(stream->perf->i915) <= 11; + stream->perf->gen8_valid_ctx_bit); } static u64 oa_timestamp(struct i915_perf_stream *stream, void *report) @@ -5096,6 +5095,7 @@ static void i915_perf_init_info(struct drm_i915_private *i915) perf->gen8_valid_ctx_bit = BIT(16); break; case 12: + perf->gen8_valid_ctx_bit = BIT(16); /* * Calculate offset at runtime in oa_pin_context for gen12 and * cache the value in perf->ctx_oactxctrl_offset.
When supporting OA for TGL, it was seen that the context valid bit in the report ID was not defined, however revisiting the spec seems to have this bit defined. The bit is used to determine if a context is valid on a context switch and is essential to determine active and idle periods for a context. Re-enable the context valid bit for gen12 platforms. Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL") Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> --- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)