diff mbox series

[1/2] drm/i915: Add helper function for getting number of VDSC engines

Message ID 20230704131758.14024-2-stanislav.lisovskiy@intel.com (mailing list archive)
State New, archived
Headers show
Series Calculate CDCLK more properly when DSC is enabled | expand

Commit Message

Stanislav Lisovskiy July 4, 2023, 1:17 p.m. UTC 
Currently we are using dsc_split and bigjoiner variables for determining
amount of VDSC instances, however that might change in future, if we happen
to have more of those.
So lets pack all that logic into single function for convenience, so that
at least this isn't hardcoded throughout the whole VDSC code.

v2: - s/u8/int/ (Jani Nikula)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++++++++++----
 drivers/gpu/drm/i915/display/intel_vdsc.h |  1 +
 2 files changed, 12 insertions(+), 4 deletions(-)

Comments

Nautiyal, Ankit K July 10, 2023, 6:10 a.m. UTC | #1 
LGTM.

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

On 7/4/2023 6:47 PM, Stanislav Lisovskiy wrote:
> Currently we are using dsc_split and bigjoiner variables for determining
> amount of VDSC instances, however that might change in future, if we happen
> to have more of those.
> So lets pack all that logic into single function for convenience, so that
> at least this isn't hardcoded throughout the whole VDSC code.
>
> v2: - s/u8/int/ (Jani Nikula)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vdsc.c | 15 +++++++++++----
>   drivers/gpu/drm/i915/display/intel_vdsc.h |  1 +
>   2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index bd9116d2cd76..530f3c08a172 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -293,6 +293,16 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>   		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
>   }
>   
> +int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
> +{
> +	int num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
> +
> +	if (crtc_state->bigjoiner_pipes)
> +		num_vdsc_instances *= 2;
> +
> +	return num_vdsc_instances;
> +}
> +
>   static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -303,11 +313,8 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
>   	u32 pps_val = 0;
>   	u32 rc_buf_thresh_dword[4];
>   	u32 rc_range_params_dword[8];
> -	u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
>   	int i = 0;
> -
> -	if (crtc_state->bigjoiner_pipes)
> -		num_vdsc_instances *= 2;
> +	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
>   
>   	/* Populate PICTURE_PARAMETER_SET_0 registers */
>   	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index 8763f00fa7e2..2cc41ff08909 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -22,6 +22,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
>   enum intel_display_power_domain
>   intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder);
>   struct intel_crtc *intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc);
> +int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state);
>   void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
>   			     const struct intel_crtc_state *crtc_state);
>   void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index bd9116d2cd76..530f3c08a172 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -293,6 +293,16 @@  intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 }
 
+int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
+{
+	int num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
+
+	if (crtc_state->bigjoiner_pipes)
+		num_vdsc_instances *= 2;
+
+	return num_vdsc_instances;
+}
+
 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -303,11 +313,8 @@  static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	u32 pps_val = 0;
 	u32 rc_buf_thresh_dword[4];
 	u32 rc_range_params_dword[8];
-	u8 num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1;
 	int i = 0;
-
-	if (crtc_state->bigjoiner_pipes)
-		num_vdsc_instances *= 2;
+	int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state);
 
 	/* Populate PICTURE_PARAMETER_SET_0 registers */
 	pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor <<
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index 8763f00fa7e2..2cc41ff08909 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -22,6 +22,7 @@  void intel_dsc_get_config(struct intel_crtc_state *crtc_state);
 enum intel_display_power_domain
 intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder);
 struct intel_crtc *intel_dsc_get_bigjoiner_secondary(const struct intel_crtc *primary_crtc);
+int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state);
 void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
 			     const struct intel_crtc_state *crtc_state);
 void intel_dsc_dp_pps_write(struct intel_encoder *encoder,