From patchwork Tue Jul 25 00:19:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andi Shyti X-Patchwork-Id: 13325463 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 10E7CC001DE for ; Tue, 25 Jul 2023 00:20:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DA02010E142; Tue, 25 Jul 2023 00:20:39 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1D10610E03D; Tue, 25 Jul 2023 00:20:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1690244437; x=1721780437; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=w+WFAosz/F5oHKYVRknXPkFsqFV6VSwHipi5CPPiLI8=; b=RrGOgiXtQ8NYM/ZTbVhhxPZ5vz527uLsxN9guHQlHr37Ys0KJWERJz3E vOx1f9yRYAwAOTwVVScnAJqobPxWz37CQLyCZNOs7tVuNTKfvabZRznlg kvX3lI61DDGBETEMLOqGySq//DrLtBwpBlt5pjbFgr0K4H3pC+xwqlLcE /pVKQupqgHIdOV1cvr4GzVVIJ0D856z624MYTI7LkK5VzinA1N95uwgUf sexwZgYRhbIV8MIjlRfsjRbBtAfBWr+WQNzLe04bSLjSx/j1kvkdwPHkB omBq4Um/Nw7HqotiEHQmy5lVwBmVSRE0vmcbRIvjU41Od3ec26+gPLiCP Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10781"; a="365043831" X-IronPort-AV: E=Sophos;i="6.01,229,1684825200"; d="scan'208";a="365043831" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2023 17:20:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10781"; a="791159996" X-IronPort-AV: E=Sophos;i="6.01,229,1684825200"; d="scan'208";a="791159996" Received: from gionescu-mobl2.ger.corp.intel.com (HELO intel.com) ([10.252.34.175]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jul 2023 17:20:33 -0700 From: Andi Shyti To: Jonathan Cavitt , Matt Roper , Chris Wilson , Mika Kuoppala , Nirmoy Das , Andrzej Hajda Date: Tue, 25 Jul 2023 02:19:46 +0200 Message-Id: <20230725001950.1014671-4-andi.shyti@linux.intel.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230725001950.1014671-1-andi.shyti@linux.intel.com> References: <20230725001950.1014671-1-andi.shyti@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v9 3/7] drm/i915/gt: Ensure memory quiesced before invalidation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx , linux-stable , dri-devel Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Jonathan Cavitt All memory traffic must be quiesced before requesting an aux invalidation on platforms that use Aux CCS. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Requires: a2a4aa0eef3b ("drm/i915: Add the gen12_needs_ccs_aux_inv helper") Signed-off-by: Jonathan Cavitt Signed-off-by: Andi Shyti Cc: # v5.8+ Reviewed-by: Nirmoy Das Reviewed-by: Andrzej Hajda --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c index 46744f9660771..58b448708e750 100644 --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c @@ -214,7 +214,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) { struct intel_engine_cs *engine = rq->engine; - if (mode & EMIT_FLUSH) { + /* + * On Aux CCS platforms the invalidation of the Aux + * table requires quiescing memory traffic beforehand + */ + if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) { u32 flags = 0; int err; u32 *cs;