| Message ID | 20230814200632.56105-20-matthew.d.roper@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Reduce MTL-specific platform checks | expand |
Quoting Matt Roper (2023-08-14 17:06:42-03:00) >Many of the IS_METEORLAKE conditions throughout the driver are supposed >to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform >specifically. Update those checks to ensure that the code will still >operate properly if/when these IP versions show up on future platforms. > >v2: > - Update two more conditions (one for pg_enable, one for MTL HuC > compatibility). > >Signed-off-by: Matt Roper <matthew.d.roper@intel.com> >--- > drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++-- > drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +- > drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- > drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- > drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- > drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 ++- > drivers/gpu/drm/i915/i915_debugfs.c | 2 +- > drivers/gpu/drm/i915/i915_perf.c | 8 +++++--- > 9 files changed, 15 insertions(+), 12 deletions(-) > >diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c >index d24c0ce8805c..19156ba4b9ef 100644 >--- a/drivers/gpu/drm/i915/gem/i915_gem_create.c >+++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c >@@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data) > BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) != > offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd)); > >- /* Limiting the extension only to Meteor Lake */ >- if (!IS_METEORLAKE(i915)) >+ /* Limiting the extension only to Xe_LPG and beyond */ >+ if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)) > return -ENODEV; > > if (copy_from_user(&ext, base, sizeof(ext))) >diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c >index b538b5c04948..e91fc881dbf1 100644 >--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c >+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c >@@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) > { > struct drm_i915_private *i915 = engine->i915; > >- if (IS_METEORLAKE(i915) && engine->id == GSC0) { >+ if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { > intel_uncore_write(engine->gt->uncore, > RC_PSMI_CTRL_GSCCS, > _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE)); >diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c >index 2c014407225c..a2d8a271fe68 100644 >--- a/drivers/gpu/drm/i915/gt/intel_mocs.c >+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c >@@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, > memset(table, 0, sizeof(struct drm_i915_mocs_table)); > > table->unused_entries_index = I915_MOCS_PTE; >- if (IS_METEORLAKE(i915)) { >+ if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) { > table->size = ARRAY_SIZE(mtl_mocs_table); > table->table = mtl_mocs_table; > table->n_entries = MTL_NUM_MOCS_ENTRIES; >diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c >index 748b0c695072..a5d725508c77 100644 >--- a/drivers/gpu/drm/i915/gt/intel_rc6.c >+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c >@@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) > * temporary wa and should be removed after fixing real cause > * of forcewake timeouts. > */ >- if (IS_METEORLAKE(gt->i915) || >+ if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || > IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || > IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) > pg_enable = >diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c >index fd6c22aeb670..98575d79c446 100644 >--- a/drivers/gpu/drm/i915/gt/intel_reset.c >+++ b/drivers/gpu/drm/i915/gt/intel_reset.c >@@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt) > > static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask) > { >- if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0)) >+ if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0)) > return false; > > if (!__HAS_ENGINE(engine_mask, GSC0)) >diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c >index 092542f53aad..4feef874e6d6 100644 >--- a/drivers/gpu/drm/i915/gt/intel_rps.c >+++ b/drivers/gpu/drm/i915/gt/intel_rps.c >@@ -1161,7 +1161,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c > { > struct drm_i915_private *i915 = rps_to_i915(rps); > >- if (IS_METEORLAKE(i915)) >+ if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) > return mtl_get_freq_caps(rps, caps); > else > return __gen6_rps_get_freq_caps(rps, caps); >diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c >index 32e27e9a2490..ba494a4a967a 100644 >--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c >+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c >@@ -850,7 +850,8 @@ int intel_uc_check_file_version(struct intel_uc_fw *uc_fw, bool *old_ver) > * not working with newer ones. This is specific to MTL and we > * don't expect it to extend to other platforms. > */ >- if (IS_METEORLAKE(gt->i915) && uc_fw->type == INTEL_UC_FW_TYPE_HUC) { >+ if (MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && >+ uc_fw->type == INTEL_UC_FW_TYPE_HUC) { The comment says the issue is specific to MTL. Can we confirm the issue is actually tied to the media gt instead of the MTL platform? * If yes, then we should update the comment as well (and maybe rename check_mtl_huc_guc_compatibility()?). * If not, then we should discard this hunk. > ret = check_mtl_huc_guc_compatibility(gt, selected); > if (ret) > return ret; >diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c >index 4de44cf1026d..7a90a2e32c9f 100644 >--- a/drivers/gpu/drm/i915/i915_debugfs.c >+++ b/drivers/gpu/drm/i915/i915_debugfs.c >@@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) > { > struct drm_i915_private *i915 = obj_to_i915(obj); > >- if (IS_METEORLAKE(i915)) { >+ if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) { > switch (obj->pat_index) { > case 0: return " WB"; > case 1: return " WT"; >diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c >index 2ef8addb0cfd..f3ab6f65a556 100644 >--- a/drivers/gpu/drm/i915/i915_perf.c >+++ b/drivers/gpu/drm/i915/i915_perf.c >@@ -3227,11 +3227,13 @@ get_sseu_config(struct intel_sseu *out_sseu, > */ > u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915) > { >+ struct intel_gt *gt = to_gt(i915); >+ > /* > * Wa_18013179988:dg2 >- * Wa_14015846243:mtl >+ * Wa_14015846243:xelpg Should we take this opportunity to use the correct lineage number (18013179988) here? -- Gustavo Sousa > */ >- if (IS_DG2(i915) || IS_METEORLAKE(i915)) { >+ if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) { > intel_wakeref_t wakeref; > u32 reg, shift; > >@@ -4539,7 +4541,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr) > > static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr) > { >- if (IS_METEORLAKE(perf->i915)) >+ if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70)) > return reg_in_range_table(addr, mtl_oa_mux_regs); > else > return reg_in_range_table(addr, gen12_oa_mux_regs); >-- >2.41.0 >
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index d24c0ce8805c..19156ba4b9ef 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -405,8 +405,8 @@ static int ext_set_pat(struct i915_user_extension __user *base, void *data) BUILD_BUG_ON(sizeof(struct drm_i915_gem_create_ext_set_pat) != offsetofend(struct drm_i915_gem_create_ext_set_pat, rsvd)); - /* Limiting the extension only to Meteor Lake */ - if (!IS_METEORLAKE(i915)) + /* Limiting the extension only to Xe_LPG and beyond */ + if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)) return -ENODEV; if (copy_from_user(&ext, base, sizeof(ext))) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c index b538b5c04948..e91fc881dbf1 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c @@ -21,7 +21,7 @@ static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) { struct drm_i915_private *i915 = engine->i915; - if (IS_METEORLAKE(i915) && engine->id == GSC0) { + if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { intel_uncore_write(engine->gt->uncore, RC_PSMI_CTRL_GSCCS, _MASKED_BIT_DISABLE(IDLE_MSG_DISABLE)); diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c index 2c014407225c..a2d8a271fe68 100644 --- a/drivers/gpu/drm/i915/gt/intel_mocs.c +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c @@ -507,7 +507,7 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915, memset(table, 0, sizeof(struct drm_i915_mocs_table)); table->unused_entries_index = I915_MOCS_PTE; - if (IS_METEORLAKE(i915)) { + if (IS_GFX_GT_IP_RANGE(&i915->gt0, IP_VER(12, 70), IP_VER(12, 71))) { table->size = ARRAY_SIZE(mtl_mocs_table); table->table = mtl_mocs_table; table->n_entries = MTL_NUM_MOCS_ENTRIES; diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c index 748b0c695072..a5d725508c77 100644 --- a/drivers/gpu/drm/i915/gt/intel_rc6.c +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c @@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6) * temporary wa and should be removed after fixing real cause * of forcewake timeouts. */ - if (IS_METEORLAKE(gt->i915) || + if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) || IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0)) pg_enable = diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c index fd6c22aeb670..98575d79c446 100644 --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c @@ -705,7 +705,7 @@ static int __reset_guc(struct intel_gt *gt) static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask) { - if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0)) + if (MEDIA_VER_FULL(gt->i915) != IP_VER(13, 0) || !HAS_ENGINE(gt, GSC0)) return false; if (!__HAS_ENGINE(engine_mask, GSC0)) diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 092542f53aad..4feef874e6d6 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -1161,7 +1161,7 @@ void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *c { struct drm_i915_private *i915 = rps_to_i915(rps); - if (IS_METEORLAKE(i915)) + if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70)) return mtl_get_freq_caps(rps, caps); else return __gen6_rps_get_freq_caps(rps, caps); diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c index 32e27e9a2490..ba494a4a967a 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c @@ -850,7 +850,8 @@ int intel_uc_check_file_version(struct intel_uc_fw *uc_fw, bool *old_ver) * not working with newer ones. This is specific to MTL and we * don't expect it to extend to other platforms. */ - if (IS_METEORLAKE(gt->i915) && uc_fw->type == INTEL_UC_FW_TYPE_HUC) { + if (MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && + uc_fw->type == INTEL_UC_FW_TYPE_HUC) { ret = check_mtl_huc_guc_compatibility(gt, selected); if (ret) return ret; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 4de44cf1026d..7a90a2e32c9f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -144,7 +144,7 @@ static const char *i915_cache_level_str(struct drm_i915_gem_object *obj) { struct drm_i915_private *i915 = obj_to_i915(obj); - if (IS_METEORLAKE(i915)) { + if (IS_GFX_GT_IP_RANGE(to_gt(i915), IP_VER(12, 70), IP_VER(12, 71))) { switch (obj->pat_index) { case 0: return " WB"; case 1: return " WT"; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 2ef8addb0cfd..f3ab6f65a556 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3227,11 +3227,13 @@ get_sseu_config(struct intel_sseu *out_sseu, */ u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915) { + struct intel_gt *gt = to_gt(i915); + /* * Wa_18013179988:dg2 - * Wa_14015846243:mtl + * Wa_14015846243:xelpg */ - if (IS_DG2(i915) || IS_METEORLAKE(i915)) { + if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) { intel_wakeref_t wakeref; u32 reg, shift; @@ -4539,7 +4541,7 @@ static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr) static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr) { - if (IS_METEORLAKE(perf->i915)) + if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70)) return reg_in_range_table(addr, mtl_oa_mux_regs); else return reg_in_range_table(addr, gen12_oa_mux_regs);
Many of the IS_METEORLAKE conditions throughout the driver are supposed to be checks for Xe_LPG and/or Xe_LPM+ IP, not for the MTL platform specifically. Update those checks to ensure that the code will still operate properly if/when these IP versions show up on future platforms. v2: - Update two more conditions (one for pg_enable, one for MTL HuC compatibility). Signed-off-by: Matt Roper <matthew.d.roper@intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_create.c | 4 ++-- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 2 +- drivers/gpu/drm/i915/gt/intel_mocs.c | 2 +- drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +- drivers/gpu/drm/i915/gt/intel_reset.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 3 ++- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 8 +++++--- 9 files changed, 15 insertions(+), 12 deletions(-)