| Message ID | 20230817161456.3857111-18-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Improve BW management on shared display links | expand |
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 686ce61e16f8d..35a9bccd68d9b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -120,15 +120,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, if (slots == -EDEADLK) return slots; - if (slots >= 0) { - ret = drm_dp_mst_atomic_check(state); - /* - * If we got slots >= 0 and we can fit those based on check - * then we can exit the loop. Otherwise keep trying. - */ - if (!ret) - break; - } + if (slots >= 0) + break; } /* We failed to find a proper bpp/timeslots, return error */
After the previous patch the BW limits on the whole MST topology will be checked after computing the state for all the streams in the topology. Accordingly remove the check during the stream's encoder compute config step, to prevent failing an atomic commit due to a BW limit, if this can be resolved only by reducing the BW of other streams on the same MST link. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-)