[v11,3/8] drm/i915/vdsc: Add func to get no. of vdsc instances per pipe

Message ID	20230823104736.495930-4-suraj.kandpal@intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <intel-gfx-bounces@lists.freedesktop.org> From: Suraj Kandpal <suraj.kandpal@intel.com> To: intel-gfx@lists.freedesktop.org Date: Wed, 23 Aug 2023 16:17:32 +0530 Message-Id: <20230823104736.495930-4-suraj.kandpal@intel.com> In-Reply-To: <20230823104736.495930-1-suraj.kandpal@intel.com> References: <20230823104736.495930-1-suraj.kandpal@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Intel-gfx] [PATCH v11 3/8] drm/i915/vdsc: Add func to get no. of vdsc instances per pipe Precedence: list Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" <intel-gfx-bounces@lists.freedesktop.org>
Series	Add DSC PPS readout \| expand [v11,0/8] Add DSC PPS readout [v11,1/8] drm/i915/vdsc: Refactor dsc register field macro [v11,2/8] drm/i915/vdsc: Add a check for dsc split cases [v11,3/8] drm/i915/vdsc: Add func to get no. of vdsc instances per pipe [v11,4/8] drm/i915/vdsc: Add function to read any PPS register [v11,5/8] drm/i915/vdsc: Add function to write in PPS register [v11,6/8] drm/i915/vdsc: Remove unused dsc registers [v11,7/8] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function [v11,8/8] drm/i915/display: Compare the readout dsc pps params

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 94af579b63d3..fbe8ce9fe1ab 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -356,9 +356,14 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder) return POWER_DOMAIN_TRANSCODER_VDSC_PW2; } +static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state) +{ + return crtc_state->dsc.dsc_split ? 2 : 1; +} + int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) { - int num_vdsc_instances = (crtc_state->dsc.dsc_split) ? 2 : 1; + int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state); if (crtc_state->bigjoiner_pipes) num_vdsc_instances *= 2; @@ -378,6 +383,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) u32 rc_range_params_dword[8]; int i = 0; int num_vdsc_instances = intel_dsc_get_num_vdsc_instances(crtc_state); + int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); /* Populate PICTURE_PARAMETER_SET_0 registers */ pps_val = DSC_VER_MAJ | vdsc_cfg->dsc_version_minor << @@ -407,14 +413,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), pps_val); @@ -431,14 +437,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe), pps_val); @@ -456,14 +462,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe), pps_val); @@ -481,14 +487,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe), pps_val); @@ -506,14 +512,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe), pps_val); @@ -531,14 +537,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe), pps_val); @@ -558,14 +564,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe), pps_val); @@ -583,14 +589,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe), pps_val); @@ -608,14 +614,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe), pps_val); @@ -633,14 +639,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe), pps_val); @@ -660,14 +666,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_10, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe), pps_val); @@ -688,14 +694,14 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) * If 2 VDSC instances are needed, configure PPS for second * VDSC */ - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_16, pps_val); } else { intel_de_write(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe), pps_val); @@ -709,7 +715,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_de_write(dev_priv, MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe), pps_val); @@ -722,7 +728,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_de_write(dev_priv, MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe), pps_val); - if (crtc_state->dsc.dsc_split) + if (vdsc_instances_per_pipe > 1) intel_de_write(dev_priv, MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe), pps_val); @@ -746,7 +752,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) rc_buf_thresh_dword[2]); intel_de_write(dev_priv, DSCA_RC_BUF_THRESH_1_UDW, rc_buf_thresh_dword[3]); - if (crtc_state->dsc.dsc_split) { + if (vdsc_instances_per_pipe > 1) { intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); intel_de_write(dev_priv, DSCC_RC_BUF_THRESH_0_UDW, @@ -765,7 +771,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) rc_buf_thresh_dword[2]); intel_de_write(dev_priv, ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe), rc_buf_thresh_dword[3]); - if (crtc_state->dsc.dsc_split) { + if (vdsc_instances_per_pipe > 1) { intel_de_write(dev_priv, ICL_DSC1_RC_BUF_THRESH_0(pipe), rc_buf_thresh_dword[0]); @@ -811,7 +817,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) rc_range_params_dword[6]); intel_de_write(dev_priv, DSCA_RC_RANGE_PARAMETERS_3_UDW, rc_range_params_dword[7]); - if (crtc_state->dsc.dsc_split) { + if (vdsc_instances_per_pipe > 1) { intel_de_write(dev_priv, DSCC_RC_RANGE_PARAMETERS_0, rc_range_params_dword[0]); intel_de_write(dev_priv, @@ -854,7 +860,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state) intel_de_write(dev_priv, ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe), rc_range_params_dword[7]); - if (crtc_state->dsc.dsc_split) { + if (vdsc_instances_per_pipe > 1) { intel_de_write(dev_priv, ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe), rc_range_params_dword[0]); @@ -960,6 +966,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; u32 dss_ctl2_val = 0; + int vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); if (!crtc_state->dsc.compression_enable) return; @@ -967,7 +974,7 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) intel_dsc_pps_configure(crtc_state); dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; - if (crtc_state->dsc.dsc_split) { + if (vdsc_instances_per_pipe > 1) { dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } @@ -1003,6 +1010,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0, pps_temp1; + int vdsc_instances_per_pipe; if (!intel_dsc_source_support(crtc_state)) return; @@ -1025,10 +1033,12 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) /* FIXME: add more state readout as needed */ + vdsc_instances_per_pipe = intel_dsc_get_vdsc_per_pipe(crtc_state); + /* PPS0 & PPS1 */ if (!is_pipe_dsc(crtc, cpu_transcoder)) { pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1); - if (crtc_state->dsc.dsc_split) { + if (vdsc_instances_per_pipe > 1) { pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1); drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1); } @@ -1037,7 +1047,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state) ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe)); pps1 = intel_de_read(dev_priv, ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); - if (crtc_state->dsc.dsc_split) { + if (vdsc_instances_per_pipe > 1) { pps_temp0 = intel_de_read(dev_priv, ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe)); pps_temp1 = intel_de_read(dev_priv,

[v11,3/8] drm/i915/vdsc: Add func to get no. of vdsc instances per pipe

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Patch