| Message ID | 20230823170740.1180212-15-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Lunar Lake display | expand |
On Wed, Aug 23, 2023 at 10:07:12AM -0700, Lucas De Marchi wrote: > From: Gustavo Sousa <gustavo.sousa@intel.com> > > LNL has south display on the same SoC. As such, define a new fake PCH > entry for it. As mentioned on the earlier patches, either matching on display IP or PICA ID might be more appropriate than matching on LNL base platform? Matt > > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++- > drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++ > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c > index cf795ecdcc26..5b9a01d26cab 100644 > --- a/drivers/gpu/drm/i915/soc/intel_pch.c > +++ b/drivers/gpu/drm/i915/soc/intel_pch.c > @@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) > * South display engine on the same PCI device: just assign the fake > * PCH. > */ > - if (IS_DG2(dev_priv)) { > + if (IS_LUNARLAKE(dev_priv)) { > + dev_priv->pch_type = PCH_LNL; > + return; > + } else if (IS_DG2(dev_priv)) { > dev_priv->pch_type = PCH_DG2; > return; > } else if (IS_DG1(dev_priv)) { > diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h > index 32aff5a70d04..1b03ea60a7a8 100644 > --- a/drivers/gpu/drm/i915/soc/intel_pch.h > +++ b/drivers/gpu/drm/i915/soc/intel_pch.h > @@ -30,6 +30,7 @@ enum intel_pch { > /* Fake PCHs, functionality handled on the same PCI dev */ > PCH_DG1 = 1024, > PCH_DG2, > + PCH_LNL, > }; > > #define INTEL_PCH_DEVICE_ID_MASK 0xff80 > @@ -66,6 +67,7 @@ enum intel_pch { > > #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) > #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) > +#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL) > #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) > #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) > #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) > -- > 2.40.1 >
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c index cf795ecdcc26..5b9a01d26cab 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.c +++ b/drivers/gpu/drm/i915/soc/intel_pch.c @@ -220,7 +220,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) * South display engine on the same PCI device: just assign the fake * PCH. */ - if (IS_DG2(dev_priv)) { + if (IS_LUNARLAKE(dev_priv)) { + dev_priv->pch_type = PCH_LNL; + return; + } else if (IS_DG2(dev_priv)) { dev_priv->pch_type = PCH_DG2; return; } else if (IS_DG1(dev_priv)) { diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h index 32aff5a70d04..1b03ea60a7a8 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.h +++ b/drivers/gpu/drm/i915/soc/intel_pch.h @@ -30,6 +30,7 @@ enum intel_pch { /* Fake PCHs, functionality handled on the same PCI dev */ PCH_DG1 = 1024, PCH_DG2, + PCH_LNL, }; #define INTEL_PCH_DEVICE_ID_MASK 0xff80 @@ -66,6 +67,7 @@ enum intel_pch { #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) +#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL) #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)