| Message ID | 20230823170740.1180212-31-lucas.demarchi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable Lunar Lake display | expand |
On Wed, Aug 23, 2023 at 10:07:28AM -0700, Lucas De Marchi wrote: > Xe2_LPD also needs workaround 15010685871. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c > index 4207863b7b2a..fdd8d04fe12c 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1839,9 +1839,9 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 > > static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) > { > - return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) && > - dev_priv->display.cdclk.hw.vco > 0 && > - HAS_CDCLK_SQUASH(dev_priv)); > + return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) || > + DISPLAY_VER(dev_priv) == 20) && We may have future 20.xx platforms for which this doesn't hold true. This should probably be a "DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0)" to exactly match Xe2_LPD and nothing else. Note that the drm-intel version of the code has already replaced the MTL check with an Xe_LPD+ version check, but that hasn't propagated to drm-xe-next yet. While we're here, we can probably re-order this too (newest platform first). Matt > + dev_priv->display.cdclk.hw.vco > 0 && HAS_CDCLK_SQUASH(dev_priv); > } > > static void _bxt_set_cdclk(struct drm_i915_private *dev_priv, > -- > 2.40.1 >
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4207863b7b2a..fdd8d04fe12c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1839,9 +1839,9 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv) { - return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) && - dev_priv->display.cdclk.hw.vco > 0 && - HAS_CDCLK_SQUASH(dev_priv)); + return (IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv) || + DISPLAY_VER(dev_priv) == 20) && + dev_priv->display.cdclk.hw.vco > 0 && HAS_CDCLK_SQUASH(dev_priv); } static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
Xe2_LPD also needs workaround 15010685871. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)