diff mbox series

[v3] drm/i915: Added Wa_18022495364

Message ID 20230908094933.4121472-1-dnyaneshwar.bhadane@intel.com (mailing list archive)
State New, archived
Headers show
Series [v3] drm/i915: Added Wa_18022495364 | expand

Commit Message

Bhadane, Dnyaneshwar Sept. 8, 2023, 9:49 a.m. UTC 
This workaround has two different implementations,
one for gen 12 to DG2 and another for DG2 and later.
BSpec: 11354, 56551

v2:
- Removed extra parentheses from the condition (Lucas)
- Fixed spacing and new line (Lucas)

v3:
- Fixed commit message.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Nemesa Garg<nemesa.garg@intel.com>
---
 drivers/gpu/drm/i915/gt/gen8_engine_cs.c    | 5 +++++
 drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 2 ++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++++
 3 files changed, 11 insertions(+)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 0143445dba83..e260defdfc23 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -271,6 +271,11 @@  int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
 			bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
 
+		/* Wa_18022495364 */
+		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70) ||
+		    IS_DG2(rq->i915))
+			bit_group_1 |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+
 		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
 		bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
 		bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 0e4c638fcbbf..4c0cb3a3d0aa 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -164,6 +164,8 @@ 
 #define GEN9_CSFE_CHICKEN1_RCS			_MMIO(0x20d4)
 #define   GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE	(1 << 2)
 #define   GEN11_ENABLE_32_PLANE_MODE		(1 << 7)
+#define GEN12_CS_DEBUG_MODE2			_MMIO(0x20d8)
+#define   GEN12_GLOBAL_DEBUG_ENABLE			BIT(6)
 
 #define GEN7_FF_SLICE_CS_CHICKEN1		_MMIO(0x20e0)
 #define   GEN9_FFSC_PERCTX_PREEMPT_CTRL		(1 << 14)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 864d41bcf6bb..efdb4bbf8083 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -712,6 +712,10 @@  static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine,
 			    GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 			    GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL);
 
+	/* Wa_18022495364 */
+	wa_masked_en(wal, GEN12_CS_DEBUG_MODE2,
+		     GEN12_GLOBAL_DEBUG_ENABLE);
+
 	/*
 	 * Wa_16011163337 - GS_TIMER
 	 *