From patchwork Tue Sep 12 16:37:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Golani, Mitulkumar Ajitkumar" X-Patchwork-Id: 13381958 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A9BA5CA0EF2 for ; Tue, 12 Sep 2023 16:43:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 03FE710E43E; Tue, 12 Sep 2023 16:43:08 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1129710E43E; Tue, 12 Sep 2023 16:43:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1694536986; x=1726072986; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Oh8PBExTXp0IyfbEj+84IljCrHILuyb5SNewicO69Ow=; b=Nhgb4gdzwAbeWQADsORmWR0ZSNM/BubNZOz4+3E+LPKC3FzHU/CQ8zhK Ullkp0u+9BMLEeR6DKZHm5M09b859t7+dYm0nEUkIbf2XUAXbbDg4I1LF bRtW+DXyqsoveTqq6xg+4TlAoKULSEW1zkpKmngX7RCzNGozW2xiFkc0b FdGk5JsCfYePEcBemhl5Va+IiH8eIU/OVWPF0UFX6igs+wWNArUNRKbnR e8MzTaS2TtZz/pMVJSYl29jRPdD/mFlI2+PDrkAnhqVbGwoov/8YM0GtB xaa+gA6iBgYU2qvIsXAWnVyQbS/F68ac7VGdKitutxP92GpWaZgB75cQc g==; X-IronPort-AV: E=McAfee;i="6600,9927,10831"; a="442446844" X-IronPort-AV: E=Sophos;i="6.02,139,1688454000"; d="scan'208";a="442446844" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Sep 2023 09:43:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10831"; a="743775715" X-IronPort-AV: E=Sophos;i="6.02,139,1688454000"; d="scan'208";a="743775715" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orsmga002.jf.intel.com with ESMTP; 12 Sep 2023 09:43:03 -0700 From: Mitul Golani To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Tue, 12 Sep 2023 22:07:30 +0530 Message-Id: <20230912163735.1075868-4-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230912163735.1075868-1-mitulkumar.ajitkumar.golani@intel.com> References: <20230912163735.1075868-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ankit Nautiyal MTL+ supports fractional compressed bits_per_pixel, with precision of 1/16. This compressed bpp is stored in U6.4 format. Accommodate this precision while computing m_n values. Signed-off-by: Ankit Nautiyal Reviewed-by: Suraj Kandpal --- drivers/gpu/drm/i915/display/intel_display.c | 6 +++++- drivers/gpu/drm/i915/display/intel_display.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 5 +++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_fdi.c | 2 +- 5 files changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index afcbdd4f105a..b37aeac961f4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2380,10 +2380,14 @@ void intel_link_compute_m_n(u16 bits_per_pixel, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable) + bool fec_enable, + bool is_dsc_fractional_bpp) { u32 data_clock = bits_per_pixel * pixel_clock; + if (is_dsc_fractional_bpp) + data_clock = DIV_ROUND_UP(bits_per_pixel * pixel_clock, 16); + if (fec_enable) data_clock = intel_dp_mode_to_fec_clock(data_clock); diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 49ac8473b988..a4c4ca3cad65 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -398,7 +398,7 @@ u8 intel_calc_active_pipes(struct intel_atomic_state *state, void intel_link_compute_m_n(u16 bpp, int nlanes, int pixel_clock, int link_clock, struct intel_link_m_n *m_n, - bool fec_enable); + bool fec_enable, bool is_dsc_fractional_bpp); u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier); enum drm_mode_status diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1891e3ead174..a359a8d65dbd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2558,7 +2558,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock, pipe_config->port_clock, &pipe_config->dp_m2_n2, - pipe_config->fec_enable); + pipe_config->fec_enable, false); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) @@ -2737,7 +2737,8 @@ intel_dp_compute_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, pipe_config->port_clock, &pipe_config->dp_m_n, - pipe_config->fec_enable); + pipe_config->fec_enable, + pipe_config->dsc.compression_enable); /* FIXME: abstract this better */ if (pipe_config->splitter.enable) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 350c561775d4..bdc6955e517b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -172,7 +172,8 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + false); crtc_state->dp_m_n.tu = slots; return 0; @@ -267,7 +268,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, adjusted_mode->crtc_clock, crtc_state->port_clock, &crtc_state->dp_m_n, - crtc_state->fec_enable); + crtc_state->fec_enable, + crtc_state->dsc.compression_enable); crtc_state->dp_m_n.tu = slots; return 0; diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index e12b46a84fa1..15fddabf7c2e 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -259,7 +259,7 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc, pipe_config->fdi_lanes = lane; intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, - link_bw, &pipe_config->fdi_m_n, false); + link_bw, &pipe_config->fdi_m_n, false, false); ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config); if (ret == -EDEADLK)