diff mbox series

[v6,2/6] drm/i915/psr: Move psr specific dpcd init into own function

Message ID 20230921061335.454818-3-animesh.manna@intel.com (mailing list archive)
State New, archived
Headers show
Series Panel replay phase1 implementation | expand

Commit Message

Manna, Animesh Sept. 21, 2023, 6:13 a.m. UTC 
From: Jouni Högander <jouni.hogander@intel.com>

This patch is preparing adding panel replay specific dpcd init.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 41 +++++++++++++-----------
 1 file changed, 23 insertions(+), 18 deletions(-)

Comments

Murthy, Arun R Oct. 4, 2023, 8:52 a.m. UTC | #1 
> -----Original Message-----
> From: Manna, Animesh <animesh.manna@intel.com>
> Sent: Thursday, September 21, 2023 11:44 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Nikula, Jani <jani.nikula@intel.com>;
> Hogander, Jouni <jouni.hogander@intel.com>; Murthy, Arun R
> <arun.r.murthy@intel.com>
> Subject: [PATCH v6 2/6] drm/i915/psr: Move psr specific dpcd init into own
> function
> 
> From: Jouni Högander <jouni.hogander@intel.com>
> 
> This patch is preparing adding panel replay specific dpcd init.
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>

Thanks and Regards,
Arun R Murthy
--------------------

>  drivers/gpu/drm/i915/display/intel_psr.c | 41 +++++++++++++-----------
>  1 file changed, 23 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 850b11f20285..71fe2e4aca85 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -474,27 +474,22 @@ static void intel_dp_get_su_granularity(struct
> intel_dp *intel_dp)
>  	intel_dp->psr.su_y_granularity = y;
>  }
> 
> -void intel_psr_init_dpcd(struct intel_dp *intel_dp)
> +static void _psr_init_dpcd(struct intel_dp *intel_dp)
>  {
> -	struct drm_i915_private *dev_priv =
> +	struct drm_i915_private *i915 =
>  		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
> 
> -	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
> -			 sizeof(intel_dp->psr_dpcd));
> -
> -	if (!intel_dp->psr_dpcd[0])
> -		return;
> -	drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version
> %x\n",
> +	drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",
>  		    intel_dp->psr_dpcd[0]);
> 
>  	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(&i915->drm,
>  			    "PSR support not currently available for this
> panel\n");
>  		return;
>  	}
> 
>  	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
> -		drm_dbg_kms(&dev_priv->drm,
> +		drm_dbg_kms(&i915->drm,
>  			    "Panel lacks power state control, PSR cannot be
> enabled\n");
>  		return;
>  	}
> @@ -503,8 +498,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  	intel_dp->psr.sink_sync_latency =
>  		intel_dp_get_sink_sync_latency(intel_dp);
> 
> -	if (DISPLAY_VER(dev_priv) >= 9 &&
> -	    (intel_dp->psr_dpcd[0] ==
> DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
> +	if (DISPLAY_VER(i915) >= 9 &&
> +	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)
> {
>  		bool y_req = intel_dp->psr_dpcd[1] &
>  			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
>  		bool alpm = intel_dp_get_alpm_status(intel_dp);
> @@ -521,14 +516,24 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
>  		 * GTC first.
>  		 */
>  		intel_dp->psr.sink_psr2_support = y_req && alpm;
> -		drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
> +		drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
>  			    intel_dp->psr.sink_psr2_support ? "" : "not ");
> +	}
> +}
> 
> -		if (intel_dp->psr.sink_psr2_support) {
> -			intel_dp->psr.colorimetry_support =
> -				intel_dp_get_colorimetry_status(intel_dp);
> -			intel_dp_get_su_granularity(intel_dp);
> -		}
> +void intel_psr_init_dpcd(struct intel_dp *intel_dp) {
> +	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp-
> >psr_dpcd,
> +			 sizeof(intel_dp->psr_dpcd));
> +
> +	if (intel_dp->psr_dpcd[0])
> +		_psr_init_dpcd(intel_dp);
> +	/* TODO: Add PR case here */
> +
> +	if (intel_dp->psr.sink_psr2_support) {
> +		intel_dp->psr.colorimetry_support =
> +			intel_dp_get_colorimetry_status(intel_dp);
> +		intel_dp_get_su_granularity(intel_dp);
>  	}
>  }
> 
> --
> 2.29.0
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 850b11f20285..71fe2e4aca85 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -474,27 +474,22 @@  static void intel_dp_get_su_granularity(struct intel_dp *intel_dp)
 	intel_dp->psr.su_y_granularity = y;
 }
 
-void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+static void _psr_init_dpcd(struct intel_dp *intel_dp)
 {
-	struct drm_i915_private *dev_priv =
+	struct drm_i915_private *i915 =
 		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
 
-	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
-			 sizeof(intel_dp->psr_dpcd));
-
-	if (!intel_dp->psr_dpcd[0])
-		return;
-	drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n",
+	drm_dbg_kms(&i915->drm, "eDP panel supports PSR version %x\n",
 		    intel_dp->psr_dpcd[0]);
 
 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "PSR support not currently available for this panel\n");
 		return;
 	}
 
 	if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) {
-		drm_dbg_kms(&dev_priv->drm,
+		drm_dbg_kms(&i915->drm,
 			    "Panel lacks power state control, PSR cannot be enabled\n");
 		return;
 	}
@@ -503,8 +498,8 @@  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 	intel_dp->psr.sink_sync_latency =
 		intel_dp_get_sink_sync_latency(intel_dp);
 
-	if (DISPLAY_VER(dev_priv) >= 9 &&
-	    (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) {
+	if (DISPLAY_VER(i915) >= 9 &&
+	    intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
 		bool y_req = intel_dp->psr_dpcd[1] &
 			     DP_PSR2_SU_Y_COORDINATE_REQUIRED;
 		bool alpm = intel_dp_get_alpm_status(intel_dp);
@@ -521,14 +516,24 @@  void intel_psr_init_dpcd(struct intel_dp *intel_dp)
 		 * GTC first.
 		 */
 		intel_dp->psr.sink_psr2_support = y_req && alpm;
-		drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n",
+		drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n",
 			    intel_dp->psr.sink_psr2_support ? "" : "not ");
+	}
+}
 
-		if (intel_dp->psr.sink_psr2_support) {
-			intel_dp->psr.colorimetry_support =
-				intel_dp_get_colorimetry_status(intel_dp);
-			intel_dp_get_su_granularity(intel_dp);
-		}
+void intel_psr_init_dpcd(struct intel_dp *intel_dp)
+{
+	drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd,
+			 sizeof(intel_dp->psr_dpcd));
+
+	if (intel_dp->psr_dpcd[0])
+		_psr_init_dpcd(intel_dp);
+	/* TODO: Add PR case here */
+
+	if (intel_dp->psr.sink_psr2_support) {
+		intel_dp->psr.colorimetry_support =
+			intel_dp_get_colorimetry_status(intel_dp);
+		intel_dp_get_su_granularity(intel_dp);
 	}
 }