| Message ID | 20231012062620.23886-1-melanie.lobo@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Support FP16 compressed formats on MTL | expand |
On Thu, Oct 12, 2023 at 11:56:20AM +0530, Melanie Lobo wrote: > MTL supports FP16 format which is a binary floating-point computer > number format that occupies 16 bits in computer memory.Platform shall > render compression in display engine to receive FP16 compressed formats. > > This kernel change was tested with IGT patch, > https://patchwork.freedesktop.org/patch/562014/ > > Test-with: 20231011095520.10768-1-melanie.lobo@intel.com > > Signed-off-by: Melanie Lobo <melanie.lobo@intel.com> > --- > drivers/gpu/drm/i915/display/intel_fb.c | 2 ++ > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +--- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c > index e7678571b0d7..868cfc75e687 100644 > --- a/drivers/gpu/drm/i915/display/intel_fb.c > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > @@ -91,6 +91,8 @@ static const struct drm_format_info gen12_ccs_formats[] = { > { .format = DRM_FORMAT_P016, .num_planes = 4, > .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, > .hsub = 2, .vsub = 2, .is_yuv = true }, > + { .format = DRM_FORMAT_XRGB16161616F, .depth = 64, .num_planes = 2, > + .char_per_block = { 4, 1}, .block_w = { 1, 2}, .block_h = { 1, 1}, .hsub = 1, .vsub = 1 }, That chars_per_block=4 doesn't look sensible for a 64bit format. And I suspect the block_w=2 for the CCS is also wrong. > }; > > /* > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 245a64332cc7..6ec5b96904c3 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -2122,9 +2122,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > case DRM_FORMAT_Y216: > case DRM_FORMAT_XVYU12_16161616: > case DRM_FORMAT_XVYU16161616: > - if (!intel_fb_is_ccs_modifier(modifier)) > - return true; > - fallthrough; > + return true; > default: > return false; > } > -- > 2.17.1
> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Thursday, October 12, 2023 6:26 PM > To: Lobo, Melanie <melanie.lobo@intel.com> > Cc: intel-gfx@lists.freedesktop.org; Heikkila, Juha-pekka <juha- > pekka.heikkila@intel.com> > Subject: Re: [Intel-gfx] [PATCH] drm/i915: Support FP16 compressed formats > on MTL > > On Thu, Oct 12, 2023 at 11:56:20AM +0530, Melanie Lobo wrote: > > MTL supports FP16 format which is a binary floating-point computer > > number format that occupies 16 bits in computer memory.Platform shall > > render compression in display engine to receive FP16 compressed formats. > > > > This kernel change was tested with IGT patch, > > https://patchwork.freedesktop.org/patch/562014/ > > > > Test-with: 20231011095520.10768-1-melanie.lobo@intel.com > > > > Signed-off-by: Melanie Lobo <melanie.lobo@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_fb.c | 2 ++ > > drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +--- > > 2 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c > > b/drivers/gpu/drm/i915/display/intel_fb.c > > index e7678571b0d7..868cfc75e687 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > @@ -91,6 +91,8 @@ static const struct drm_format_info > gen12_ccs_formats[] = { > > { .format = DRM_FORMAT_P016, .num_planes = 4, > > .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, > 1, 1, 1 }, > > .hsub = 2, .vsub = 2, .is_yuv = true }, > > + { .format = DRM_FORMAT_XRGB16161616F, .depth = 64, > .num_planes = 2, > > + .char_per_block = { 4, 1}, .block_w = { 1, 2}, .block_h = { 1, 1}, > > +.hsub = 1, .vsub = 1 }, > > That chars_per_block=4 doesn't look sensible for a 64bit format. > And I suspect the block_w=2 for the CCS is also wrong. > > > }; > > > > /* > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > index 245a64332cc7..6ec5b96904c3 100644 > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > @@ -2122,9 +2122,7 @@ static bool > gen12_plane_format_mod_supported(struct drm_plane *_plane, > > case DRM_FORMAT_Y216: > > case DRM_FORMAT_XVYU12_16161616: > > case DRM_FORMAT_XVYU16161616: > > - if (!intel_fb_is_ccs_modifier(modifier)) > > - return true; > > - fallthrough; > > + return true; > > default: > > return false; > > } > > -- > > 2.17.1 > > -- > Ville Syrjälä > Intel Hi Ville, Thanks for your reply. I have made respective changes and floated the rev 4 series. Please take a look. Regards, Melanie lobo
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index e7678571b0d7..868cfc75e687 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -91,6 +91,8 @@ static const struct drm_format_info gen12_ccs_formats[] = { { .format = DRM_FORMAT_P016, .num_planes = 4, .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_XRGB16161616F, .depth = 64, .num_planes = 2, + .char_per_block = { 4, 1}, .block_w = { 1, 2}, .block_h = { 1, 1}, .hsub = 1, .vsub = 1 }, }; /* diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 245a64332cc7..6ec5b96904c3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2122,9 +2122,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_Y216: case DRM_FORMAT_XVYU12_16161616: case DRM_FORMAT_XVYU16161616: - if (!intel_fb_is_ccs_modifier(modifier)) - return true; - fallthrough; + return true; default: return false; }
MTL supports FP16 format which is a binary floating-point computer number format that occupies 16 bits in computer memory.Platform shall render compression in display engine to receive FP16 compressed formats. This kernel change was tested with IGT patch, https://patchwork.freedesktop.org/patch/562014/ Test-with: 20231011095520.10768-1-melanie.lobo@intel.com Signed-off-by: Melanie Lobo <melanie.lobo@intel.com> --- drivers/gpu/drm/i915/display/intel_fb.c | 2 ++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +--- 2 files changed, 3 insertions(+), 3 deletions(-)