| Message ID | 20231103093259.59054-1-mika.kahola@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier | expand |
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Friday, November 3, 2023 1:37 PM
To: Kahola, Mika <mika.kahola@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier (rev3)
Patch Details
Series:
drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier (rev3)
URL:
https://patchwork.freedesktop.org/series/125558/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/index.html
CI Bug Log - changes from CI_DRM_13833 -> Patchwork_125558v3
Summary
FAILURE
Serious unknown changes coming with Patchwork_125558v3 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125558v3, please notify your bug team (lgci.bug.filing@intel.com<mailto:lgci.bug.filing@intel.com>) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/index.html
Participating hosts (37 -> 38)
Additional (3): bat-kbl-2 bat-adlp-6 fi-bsw-n3050
Missing (2): bat-adls-5 fi-snb-2520m
Possible new issues
Here are the unknown changes that may have been introduced in Patchwork_125558v3:
IGT changes
Possible regressions
* igt@dmabuf@all-tests@dma_fence_chain:
* fi-hsw-4770: NOTRUN -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/igt@dmabuf@all-tests@dma_fence_chain.html>
The patch doesn’t touch hsw. This is false positive regression. Maybe we can rerun BAT?
-Mika-
Known issues
Here are the changes found in Patchwork_125558v3 that come from known issues:
CI changes
Possible fixes
* boot:
* fi-hsw-4770: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-hsw-4770/boot.html> (i915#8293<https://gitlab.freedesktop.org/drm/intel/issues/8293>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/boot.html>
IGT changes
Issues hit
* igt@debugfs_test@basic-hwmon:
* bat-adlp-6: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@debugfs_test@basic-hwmon.html> (i915#9318<https://gitlab.freedesktop.org/drm/intel/issues/9318>)
* igt@fbdev@info:
* bat-kbl-2: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-kbl-2/igt@fbdev@info.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#1849<https://gitlab.freedesktop.org/drm/intel/issues/1849>)
* igt@gem_lmem_swapping@parallel-random-engines:
* bat-kbl-2: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-kbl-2/igt@gem_lmem_swapping@parallel-random-engines.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +39 other tests skip
* igt@gem_lmem_swapping@random-engines:
* fi-bsw-n3050: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +18 other tests skip
* igt@gem_tiled_pread_basic:
* bat-adlp-6: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@gem_tiled_pread_basic.html> (i915#3282<https://gitlab.freedesktop.org/drm/intel/issues/3282>)
* igt@i915_selftest@live@gt_heartbeat:
* fi-glk-j4005: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html> -> DMESG-FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html> (i915#5334<https://gitlab.freedesktop.org/drm/intel/issues/5334>)
* igt@i915_selftest@live@hangcheck:
* fi-skl-guc: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-skl-guc/igt@i915_selftest@live@hangcheck.html> -> DMESG-FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-skl-guc/igt@i915_selftest@live@hangcheck.html> (i915#9549<https://gitlab.freedesktop.org/drm/intel/issues/9549>)
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
* fi-hsw-4770: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#5190<https://gitlab.freedesktop.org/drm/intel/issues/5190>)
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
* bat-adlp-6: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html> (i915#4103<https://gitlab.freedesktop.org/drm/intel/issues/4103> / i915#5608<https://gitlab.freedesktop.org/drm/intel/issues/5608>) +1 other test skip
* igt@kms_dsc@dsc-basic:
* bat-adlp-6: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@kms_dsc@dsc-basic.html> (i915#3555<https://gitlab.freedesktop.org/drm/intel/issues/3555> / i915#3840<https://gitlab.freedesktop.org/drm/intel/issues/3840>)
* igt@kms_force_connector_basic@force-load-detect:
* bat-adlp-6: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/bat-adlp-6/igt@kms_force_connector_basic@force-load-detect.html> (fdo#109285<https://bugs.freedesktop.org/show_bug.cgi?id=109285>)
* igt@kms_hdmi_inject@inject-audio:
* fi-bsw-n3050: NOTRUN -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-bsw-n3050/igt@kms_hdmi_inject@inject-audio.html> (IGT#3<https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3>)
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1:
* fi-hsw-4770: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +12 other tests skip
* igt@kms_psr@sprite_plane_onoff:
* fi-hsw-4770: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / i915#1072<https://gitlab.freedesktop.org/drm/intel/issues/1072>) +3 other tests skip
Possible fixes
* igt@dmabuf@all-tests@dma_fence:
* fi-pnv-d510: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html> -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-pnv-d510/igt@dmabuf@all-tests@dma_fence.html>
* igt@dmabuf@all-tests@sanitycheck:
* fi-pnv-d510: ABORT<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13833/fi-pnv-d510/igt@dmabuf@all-tests@sanitycheck.html> -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125558v3/fi-pnv-d510/igt@dmabuf@all-tests@sanitycheck.html>
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
Build changes
* Linux: CI_DRM_13833 -> Patchwork_125558v3
CI-20190529: 20190529
CI_DRM_13833: b978573539a590501c843a520bfc65b830d10eba @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7571: 9b79b510e53d913da5d23e86f3baa6c58a2feed8 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_125558v3: b978573539a590501c843a520bfc65b830d10eba @ git://anongit.freedesktop.org/gfx-ci/linux
Linux commits
2a6a9d2ee137 drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier
On Fri, 2023-11-03 at 11:32 +0200, Mika Kahola wrote: > Display driver shall read DPCD 00071h[3:1] during configuration > to get PSR setup time. This register provides the setup time > requirement on the VSC SDP entry packet. If setup time cannot be > met with the current timings > (e.g., PSR setup time + other blanking requirements > blanking time), > driver should enable sending VSC SDP one frame earlier before sending > the capture frame. > > BSpec: 69895 (PSR Entry Setup Frames 17:16) > > v2: Write frames before su entry to correct register (Ville, Jouni) > Move frames before su entry calculation to it's > own function (Ville, Jouni) > Rename PSR Entry Setup Frames register to indicate > Lunarlake specificity (Jouni) > v3: Modify setup entry frames calculation function to > return the actual frames (Ville) > Match comment with actual implementation (Jouni) > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_psr.c | 82 +++++++++++++++-- > -- > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 + > 3 files changed, 71 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 047fe3f8905a..92f06d67fd1e 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1708,6 +1708,7 @@ struct intel_psr { > u32 dc3co_exitline; > u32 dc3co_exit_delay; > struct delayed_work dc3co_work; > + u8 entry_setup_frames; > }; > > struct intel_dp { > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index ecd24a0b86cb..497e4c26f4a6 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -592,6 +592,9 @@ static void intel_psr_enable_sink(struct intel_dp > *intel_dp) > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; > > + if (intel_dp->psr.entry_setup_frames > 0) > + dpcd_val |= DP_PSR_FRAME_CAPTURE; > + > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); > @@ -690,6 +693,9 @@ static void hsw_activate_psr1(struct intel_dp > *intel_dp) > if (DISPLAY_VER(dev_priv) >= 8) > val |= EDP_PSR_CRC_ENABLE; > > + if (DISPLAY_VER(dev_priv) >= 20) > + val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > >psr.entry_setup_frames); > + > intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), > ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); > } > @@ -727,11 +733,27 @@ static int psr2_block_count(struct intel_dp > *intel_dp) > return psr2_block_count_lines(intel_dp) / 4; > } > > +static u8 get_frames_before_su_entry(struct intel_dp *intel_dp) > +{ > + u8 frames_before_su_entry; > + > + frames_before_su_entry = max_t(u8, > + intel_dp- > >psr.sink_sync_latency + 1, > + 2); > + > + /* Entry setup frames must be at least 1 less than frames > before SU entry */ > + if (intel_dp->psr.entry_setup_frames >= > frames_before_su_entry) > + frames_before_su_entry = intel_dp- > >psr.entry_setup_frames + 1; > + > + return frames_before_su_entry; > +} > + > static void hsw_activate_psr2(struct intel_dp *intel_dp) > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > u32 val = EDP_PSR2_ENABLE; > + u32 psr_val = 0; > > val |= > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); > > @@ -741,7 +763,8 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= > 12) > val |= EDP_Y_COORDINATE_ENABLE; > > - val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp- > >psr.sink_sync_latency + 1, 2)); > + val |= > EDP_PSR2_FRAME_BEFORE_SU(get_frames_before_su_entry(intel_dp)); > + > val |= intel_psr2_get_tp_time(intel_dp); > > if (DISPLAY_VER(dev_priv) >= 12) { > @@ -785,6 +808,9 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > val |= EDP_PSR2_SU_SDP_SCANLINE; > > + if (DISPLAY_VER(dev_priv) >= 20) > + psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > >psr.entry_setup_frames); > + > if (intel_dp->psr.psr2_sel_fetch_enabled) { > u32 tmp; > > @@ -798,7 +824,7 @@ static void hsw_activate_psr2(struct intel_dp > *intel_dp) > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec > is > * recommending keep this bit unset while PSR2 is enabled. > */ > - intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > cpu_transcoder), 0); > + intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > cpu_transcoder), psr_val); > > intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); > } > @@ -1066,6 +1092,40 @@ static bool _compute_psr2_wake_times(struct > intel_dp *intel_dp, > return true; > } > > +static u8 intel_psr_set_entry_setup_frames(struct intel_dp > *intel_dp, > + const struct > drm_display_mode *adjusted_mode) I think "set" is not correct here. intel_psr_get_entry_setup_frames is more appropriate. > +{ > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); You should use name i915 here. > + int psr_setup_time = drm_dp_psr_setup_time(intel_dp- > >psr_dpcd); > + u8 entry_setup_frames = 0; > + > + if (psr_setup_time < 0) { > + drm_dbg_kms(&dev_priv->drm, > + "PSR condition failed: Invalid PSR setup > time (0x%02x)\n", > + intel_dp->psr_dpcd[1]); > + return -ETIME; > + } > + > + > + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > - 1) { > + if (DISPLAY_VER(dev_priv) >= 20) { > + /* setup entry frames can be set up to 3 > frames */ > + entry_setup_frames = 1; > + drm_dbg_kms(&dev_priv->drm, > + "PSR setup entry frames set to > %d\n", > + entry_setup_frames); Don't refer "setting" here as this is just returning the value. Not setting it. BR, Jouni Högander > + } else { > + drm_dbg_kms(&dev_priv->drm, > + "PSR condition failed: PSR setup > time (%d us) too long\n", > + psr_setup_time); > + return -ETIME; > + } > + } > + > + return entry_setup_frames; > +} > + > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > struct intel_crtc_state > *crtc_state) > { > @@ -1213,7 +1273,7 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > const struct drm_display_mode *adjusted_mode = > &crtc_state->hw.adjusted_mode; > - int psr_setup_time; > + u8 entry_setup_frames; > > /* > * Current PSR panels don't work reliably with VRR enabled > @@ -1242,19 +1302,13 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > return; > } > > - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); > - if (psr_setup_time < 0) { > - drm_dbg_kms(&dev_priv->drm, > - "PSR condition failed: Invalid PSR setup > time (0x%02x)\n", > - intel_dp->psr_dpcd[1]); > - return; > - } > + entry_setup_frames = > intel_psr_set_entry_setup_frames(intel_dp, adjusted_mode); > > - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > - 1) { > + if (entry_setup_frames >= 0) { > + intel_dp->psr.entry_setup_frames = > entry_setup_frames; > + } else { > drm_dbg_kms(&dev_priv->drm, > - "PSR condition failed: PSR setup time (%d > us) too long\n", > - psr_setup_time); > + "PSR condition failed: PSR setup timing > not met\n"); > return; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > index d39951383c92..efe4306b37e0 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > @@ -35,6 +35,8 @@ > #define > EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ > ENTRY_TIME_MASK, 3) > #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) > #define > EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP > _TIME_MASK, (x)) > +#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) > +#define > LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY > _SETUP_FRAMES_MASK, (x)) > #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) > #define EDP_PSR_TP_MASK REG_BIT(11) > #define > EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, > 0)
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Monday, November 6, 2023 10:41 AM > To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org > Cc: ville.syrjala@linux.intel.com > Subject: Re: [PATCH v3] drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier > > On Fri, 2023-11-03 at 11:32 +0200, Mika Kahola wrote: > > Display driver shall read DPCD 00071h[3:1] during configuration to get > > PSR setup time. This register provides the setup time requirement on > > the VSC SDP entry packet. If setup time cannot be met with the current > > timings (e.g., PSR setup time + other blanking requirements > blanking > > time), driver should enable sending VSC SDP one frame earlier before > > sending the capture frame. > > > > BSpec: 69895 (PSR Entry Setup Frames 17:16) > > > > v2: Write frames before su entry to correct register (Ville, Jouni) > > Move frames before su entry calculation to it's > > own function (Ville, Jouni) > > Rename PSR Entry Setup Frames register to indicate > > Lunarlake specificity (Jouni) > > v3: Modify setup entry frames calculation function to > > return the actual frames (Ville) > > Match comment with actual implementation (Jouni) > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > --- > > .../drm/i915/display/intel_display_types.h | 1 + > > drivers/gpu/drm/i915/display/intel_psr.c | 82 +++++++++++++++-- > > -- > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 + > > 3 files changed, 71 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 047fe3f8905a..92f06d67fd1e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1708,6 +1708,7 @@ struct intel_psr { > > u32 dc3co_exitline; > > u32 dc3co_exit_delay; > > struct delayed_work dc3co_work; > > + u8 entry_setup_frames; > > }; > > > > struct intel_dp { > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index ecd24a0b86cb..497e4c26f4a6 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -592,6 +592,9 @@ static void intel_psr_enable_sink(struct intel_dp > > *intel_dp) > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; > > > > + if (intel_dp->psr.entry_setup_frames > 0) > > + dpcd_val |= DP_PSR_FRAME_CAPTURE; > > + > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D0); @@ -690,6 +693,9 @@ static void > > hsw_activate_psr1(struct intel_dp > > *intel_dp) > > if (DISPLAY_VER(dev_priv) >= 8) > > val |= EDP_PSR_CRC_ENABLE; > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > + val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > >psr.entry_setup_frames); > > + > > intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), > > ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); > > } > > @@ -727,11 +733,27 @@ static int psr2_block_count(struct intel_dp > > *intel_dp) > > return psr2_block_count_lines(intel_dp) / 4; > > } > > > > +static u8 get_frames_before_su_entry(struct intel_dp *intel_dp) { > > + u8 frames_before_su_entry; > > + > > + frames_before_su_entry = max_t(u8, > > + intel_dp- > > >psr.sink_sync_latency + 1, > > + 2); > > + > > + /* Entry setup frames must be at least 1 less than frames > > before SU entry */ > > + if (intel_dp->psr.entry_setup_frames >= > > frames_before_su_entry) > > + frames_before_su_entry = intel_dp- > > >psr.entry_setup_frames + 1; > > + > > + return frames_before_su_entry; } > > + > > static void hsw_activate_psr2(struct intel_dp *intel_dp) > > { > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > > u32 val = EDP_PSR2_ENABLE; > > + u32 psr_val = 0; > > > > val |= > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); > > > > @@ -741,7 +763,8 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= > > 12) > > val |= EDP_Y_COORDINATE_ENABLE; > > > > - val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp- > > >psr.sink_sync_latency + 1, 2)); > > + val |= > > EDP_PSR2_FRAME_BEFORE_SU(get_frames_before_su_entry(intel_dp)); > > + > > val |= intel_psr2_get_tp_time(intel_dp); > > > > if (DISPLAY_VER(dev_priv) >= 12) { @@ -785,6 +808,9 @@ static > > void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > val |= EDP_PSR2_SU_SDP_SCANLINE; > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > + psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > >psr.entry_setup_frames); > > + > > if (intel_dp->psr.psr2_sel_fetch_enabled) { > > u32 tmp; > > > > @@ -798,7 +824,7 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec > > is > > * recommending keep this bit unset while PSR2 is enabled. > > */ > > - intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > cpu_transcoder), 0); > > + intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > cpu_transcoder), psr_val); > > > > intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); > > } > > @@ -1066,6 +1092,40 @@ static bool _compute_psr2_wake_times(struct > > intel_dp *intel_dp, > > return true; > > } > > > > +static u8 intel_psr_set_entry_setup_frames(struct intel_dp > > *intel_dp, > > + const struct > > drm_display_mode *adjusted_mode) > > I think "set" is not correct here. intel_psr_get_entry_setup_frames is more appropriate. Probably so. I was thinking setting the register with this value but here it's more getting the value than setting. > > > +{ > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > You should use name i915 here. Right. I'll fix this. > > > + int psr_setup_time = drm_dp_psr_setup_time(intel_dp- > > >psr_dpcd); > > + u8 entry_setup_frames = 0; > > + > > + if (psr_setup_time < 0) { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR condition failed: Invalid PSR setup > > time (0x%02x)\n", > > + intel_dp->psr_dpcd[1]); > > + return -ETIME; > > + } > > + > > + > > + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > > - 1) { > > + if (DISPLAY_VER(dev_priv) >= 20) { > > + /* setup entry frames can be set up to 3 > > frames */ > > + entry_setup_frames = 1; > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR setup entry frames set to > > %d\n", > > + entry_setup_frames); > > Don't refer "setting" here as this is just returning the value. Not setting it. I'll drop the "set" here. Thanks for the comments and review! -Mika- > > BR, > > Jouni Högander > > > + } else { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR condition failed: PSR setup > > time (%d us) too long\n", > > + psr_setup_time); > > + return -ETIME; > > + } > > + } > > + > > + return entry_setup_frames; > > +} > > + > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > struct intel_crtc_state > > *crtc_state) > > { > > @@ -1213,7 +1273,7 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > const struct drm_display_mode *adjusted_mode = > > &crtc_state->hw.adjusted_mode; > > - int psr_setup_time; > > + u8 entry_setup_frames; > > > > /* > > * Current PSR panels don't work reliably with VRR enabled @@ > > -1242,19 +1302,13 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > return; > > } > > > > - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); > > - if (psr_setup_time < 0) { > > - drm_dbg_kms(&dev_priv->drm, > > - "PSR condition failed: Invalid PSR setup > > time (0x%02x)\n", > > - intel_dp->psr_dpcd[1]); > > - return; > > - } > > + entry_setup_frames = > > intel_psr_set_entry_setup_frames(intel_dp, adjusted_mode); > > > > - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > > - 1) { > > + if (entry_setup_frames >= 0) { > > + intel_dp->psr.entry_setup_frames = > > entry_setup_frames; > > + } else { > > drm_dbg_kms(&dev_priv->drm, > > - "PSR condition failed: PSR setup time (%d > > us) too long\n", > > - psr_setup_time); > > + "PSR condition failed: PSR setup timing > > not met\n"); > > return; > > } > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > index d39951383c92..efe4306b37e0 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > @@ -35,6 +35,8 @@ > > #define > > EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ > > ENTRY_TIME_MASK, 3) > > #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) > > #define > > EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP > > _TIME_MASK, (x)) > > +#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) > > +#define > > LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY > > _SETUP_FRAMES_MASK, (x)) > > #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) > > #define EDP_PSR_TP_MASK REG_BIT(11) > > #define > > EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, > > 0)
On Mon, Nov 06, 2023 at 08:40:52AM +0000, Hogander, Jouni wrote: > On Fri, 2023-11-03 at 11:32 +0200, Mika Kahola wrote: > > Display driver shall read DPCD 00071h[3:1] during configuration > > to get PSR setup time. This register provides the setup time > > requirement on the VSC SDP entry packet. If setup time cannot be > > met with the current timings > > (e.g., PSR setup time + other blanking requirements > blanking time), > > driver should enable sending VSC SDP one frame earlier before sending > > the capture frame. > > > > BSpec: 69895 (PSR Entry Setup Frames 17:16) > > > > v2: Write frames before su entry to correct register (Ville, Jouni) > > Move frames before su entry calculation to it's > > own function (Ville, Jouni) > > Rename PSR Entry Setup Frames register to indicate > > Lunarlake specificity (Jouni) > > v3: Modify setup entry frames calculation function to > > return the actual frames (Ville) > > Match comment with actual implementation (Jouni) > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > --- > > .../drm/i915/display/intel_display_types.h | 1 + > > drivers/gpu/drm/i915/display/intel_psr.c | 82 +++++++++++++++-- > > -- > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 + > > 3 files changed, 71 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 047fe3f8905a..92f06d67fd1e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1708,6 +1708,7 @@ struct intel_psr { > > u32 dc3co_exitline; > > u32 dc3co_exit_delay; > > struct delayed_work dc3co_work; > > + u8 entry_setup_frames; > > }; > > > > struct intel_dp { > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index ecd24a0b86cb..497e4c26f4a6 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -592,6 +592,9 @@ static void intel_psr_enable_sink(struct intel_dp > > *intel_dp) > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; > > > > + if (intel_dp->psr.entry_setup_frames > 0) > > + dpcd_val |= DP_PSR_FRAME_CAPTURE; > > + > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D0); > > @@ -690,6 +693,9 @@ static void hsw_activate_psr1(struct intel_dp > > *intel_dp) > > if (DISPLAY_VER(dev_priv) >= 8) > > val |= EDP_PSR_CRC_ENABLE; > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > + val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > >psr.entry_setup_frames); > > + > > intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), > > ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); > > } > > @@ -727,11 +733,27 @@ static int psr2_block_count(struct intel_dp > > *intel_dp) > > return psr2_block_count_lines(intel_dp) / 4; > > } > > > > +static u8 get_frames_before_su_entry(struct intel_dp *intel_dp) > > +{ > > + u8 frames_before_su_entry; > > + > > + frames_before_su_entry = max_t(u8, > > + intel_dp- > > >psr.sink_sync_latency + 1, > > + 2); > > + > > + /* Entry setup frames must be at least 1 less than frames > > before SU entry */ > > + if (intel_dp->psr.entry_setup_frames >= > > frames_before_su_entry) > > + frames_before_su_entry = intel_dp- > > >psr.entry_setup_frames + 1; > > + > > + return frames_before_su_entry; > > +} > > + > > static void hsw_activate_psr2(struct intel_dp *intel_dp) > > { > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > > u32 val = EDP_PSR2_ENABLE; > > + u32 psr_val = 0; > > > > val |= > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); > > > > @@ -741,7 +763,8 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= > > 12) > > val |= EDP_Y_COORDINATE_ENABLE; > > > > - val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp- > > >psr.sink_sync_latency + 1, 2)); > > + val |= > > EDP_PSR2_FRAME_BEFORE_SU(get_frames_before_su_entry(intel_dp)); > > + > > val |= intel_psr2_get_tp_time(intel_dp); > > > > if (DISPLAY_VER(dev_priv) >= 12) { > > @@ -785,6 +808,9 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > val |= EDP_PSR2_SU_SDP_SCANLINE; > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > + psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > >psr.entry_setup_frames); > > + > > if (intel_dp->psr.psr2_sel_fetch_enabled) { > > u32 tmp; > > > > @@ -798,7 +824,7 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec > > is > > * recommending keep this bit unset while PSR2 is enabled. > > */ > > - intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > cpu_transcoder), 0); > > + intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > cpu_transcoder), psr_val); > > > > intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); > > } > > @@ -1066,6 +1092,40 @@ static bool _compute_psr2_wake_times(struct > > intel_dp *intel_dp, > > return true; > > } > > > > +static u8 intel_psr_set_entry_setup_frames(struct intel_dp > > *intel_dp, > > + const struct > > drm_display_mode *adjusted_mode) > > I think "set" is not correct here. intel_psr_get_entry_setup_frames is > more appropriate. I don't really like either. We don't generally say eg. get_sin(x) either, it's just sin(x). So IMO the correct name would be just intel_psr_entry_setup_frames(), or perhaps intel_psr_num_entry_setup_frames(). That will make the code more like proper English when you read it outloud. > > > +{ > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > You should use name i915 here. > > > + int psr_setup_time = drm_dp_psr_setup_time(intel_dp- > > >psr_dpcd); > > + u8 entry_setup_frames = 0; > > + > > + if (psr_setup_time < 0) { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR condition failed: Invalid PSR setup > > time (0x%02x)\n", > > + intel_dp->psr_dpcd[1]); > > + return -ETIME; > > + } > > + > > + > > + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > > - 1) { > > + if (DISPLAY_VER(dev_priv) >= 20) { > > + /* setup entry frames can be set up to 3 > > frames */ > > + entry_setup_frames = 1; > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR setup entry frames set to > > %d\n", > > + entry_setup_frames); > > Don't refer "setting" here as this is just returning the value. Not > setting it. This kind of stuff should really all be moved to the crtc state proper, and then just dumped alongside everything else. > > BR, > > Jouni Högander > > > + } else { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR condition failed: PSR setup > > time (%d us) too long\n", > > + psr_setup_time); > > + return -ETIME; > > + } > > + } > > + > > + return entry_setup_frames; > > +} > > + > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > struct intel_crtc_state > > *crtc_state) > > { > > @@ -1213,7 +1273,7 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > const struct drm_display_mode *adjusted_mode = > > &crtc_state->hw.adjusted_mode; > > - int psr_setup_time; > > + u8 entry_setup_frames; > > > > /* > > * Current PSR panels don't work reliably with VRR enabled > > @@ -1242,19 +1302,13 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > return; > > } > > > > - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); > > - if (psr_setup_time < 0) { > > - drm_dbg_kms(&dev_priv->drm, > > - "PSR condition failed: Invalid PSR setup > > time (0x%02x)\n", > > - intel_dp->psr_dpcd[1]); > > - return; > > - } > > + entry_setup_frames = > > intel_psr_set_entry_setup_frames(intel_dp, adjusted_mode); > > > > - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > > - 1) { > > + if (entry_setup_frames >= 0) { > > + intel_dp->psr.entry_setup_frames = > > entry_setup_frames; > > + } else { > > drm_dbg_kms(&dev_priv->drm, > > - "PSR condition failed: PSR setup time (%d > > us) too long\n", > > - psr_setup_time); > > + "PSR condition failed: PSR setup timing > > not met\n"); > > return; > > } > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > index d39951383c92..efe4306b37e0 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > @@ -35,6 +35,8 @@ > > #define > > EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ > > ENTRY_TIME_MASK, 3) > > #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) > > #define > > EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP > > _TIME_MASK, (x)) > > +#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) > > +#define > > LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY > > _SETUP_FRAMES_MASK, (x)) > > #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) > > #define EDP_PSR_TP_MASK REG_BIT(11) > > #define > > EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, > > 0) >
> -----Original Message----- > From: Hogander, Jouni <jouni.hogander@intel.com> > Sent: Monday, November 6, 2023 10:41 AM > To: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org > Cc: ville.syrjala@linux.intel.com > Subject: Re: [PATCH v3] drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier > > On Fri, 2023-11-03 at 11:32 +0200, Mika Kahola wrote: > > Display driver shall read DPCD 00071h[3:1] during configuration to get > > PSR setup time. This register provides the setup time requirement on > > the VSC SDP entry packet. If setup time cannot be met with the current > > timings (e.g., PSR setup time + other blanking requirements > blanking > > time), driver should enable sending VSC SDP one frame earlier before > > sending the capture frame. > > > > BSpec: 69895 (PSR Entry Setup Frames 17:16) > > > > v2: Write frames before su entry to correct register (Ville, Jouni) > > Move frames before su entry calculation to it's > > own function (Ville, Jouni) > > Rename PSR Entry Setup Frames register to indicate > > Lunarlake specificity (Jouni) > > v3: Modify setup entry frames calculation function to > > return the actual frames (Ville) > > Match comment with actual implementation (Jouni) > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > --- > > .../drm/i915/display/intel_display_types.h | 1 + > > drivers/gpu/drm/i915/display/intel_psr.c | 82 +++++++++++++++-- > > -- > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 + > > 3 files changed, 71 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 047fe3f8905a..92f06d67fd1e 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1708,6 +1708,7 @@ struct intel_psr { > > u32 dc3co_exitline; > > u32 dc3co_exit_delay; > > struct delayed_work dc3co_work; > > + u8 entry_setup_frames; > > }; > > > > struct intel_dp { > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index ecd24a0b86cb..497e4c26f4a6 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -592,6 +592,9 @@ static void intel_psr_enable_sink(struct intel_dp > > *intel_dp) > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; > > > > + if (intel_dp->psr.entry_setup_frames > 0) > > + dpcd_val |= DP_PSR_FRAME_CAPTURE; > > + > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D0); @@ -690,6 +693,9 @@ static void > > hsw_activate_psr1(struct intel_dp > > *intel_dp) > > if (DISPLAY_VER(dev_priv) >= 8) > > val |= EDP_PSR_CRC_ENABLE; > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > + val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > >psr.entry_setup_frames); > > + > > intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), > > ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); > > } > > @@ -727,11 +733,27 @@ static int psr2_block_count(struct intel_dp > > *intel_dp) > > return psr2_block_count_lines(intel_dp) / 4; > > } > > > > +static u8 get_frames_before_su_entry(struct intel_dp *intel_dp) { > > + u8 frames_before_su_entry; > > + > > + frames_before_su_entry = max_t(u8, > > + intel_dp- > > >psr.sink_sync_latency + 1, > > + 2); > > + > > + /* Entry setup frames must be at least 1 less than frames > > before SU entry */ > > + if (intel_dp->psr.entry_setup_frames >= > > frames_before_su_entry) > > + frames_before_su_entry = intel_dp- > > >psr.entry_setup_frames + 1; > > + > > + return frames_before_su_entry; } > > + > > static void hsw_activate_psr2(struct intel_dp *intel_dp) > > { > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > > u32 val = EDP_PSR2_ENABLE; > > + u32 psr_val = 0; > > > > val |= > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); > > > > @@ -741,7 +763,8 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= > > 12) > > val |= EDP_Y_COORDINATE_ENABLE; > > > > - val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp- > > >psr.sink_sync_latency + 1, 2)); > > + val |= > > EDP_PSR2_FRAME_BEFORE_SU(get_frames_before_su_entry(intel_dp)); > > + > > val |= intel_psr2_get_tp_time(intel_dp); > > > > if (DISPLAY_VER(dev_priv) >= 12) { @@ -785,6 +808,9 @@ static > > void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > val |= EDP_PSR2_SU_SDP_SCANLINE; > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > + psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > >psr.entry_setup_frames); > > + > > if (intel_dp->psr.psr2_sel_fetch_enabled) { > > u32 tmp; > > > > @@ -798,7 +824,7 @@ static void hsw_activate_psr2(struct intel_dp > > *intel_dp) > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec > > is > > * recommending keep this bit unset while PSR2 is enabled. > > */ > > - intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > cpu_transcoder), 0); > > + intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > cpu_transcoder), psr_val); > > > > intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); > > } > > @@ -1066,6 +1092,40 @@ static bool _compute_psr2_wake_times(struct > > intel_dp *intel_dp, > > return true; > > } > > > > +static u8 intel_psr_set_entry_setup_frames(struct intel_dp > > *intel_dp, > > + const struct > > drm_display_mode *adjusted_mode) > > I think "set" is not correct here. intel_psr_get_entry_setup_frames is more appropriate. I was thinking that this we would set the register value with this value but since we do not set the actual register here, the naming is not the best possible. I will switch to use "get" instead of "set". > > > +{ > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > You should use name i915 here. Yes, we should use i915 nowadays. > > > + int psr_setup_time = drm_dp_psr_setup_time(intel_dp- > > >psr_dpcd); > > + u8 entry_setup_frames = 0; > > + > > + if (psr_setup_time < 0) { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR condition failed: Invalid PSR setup > > time (0x%02x)\n", > > + intel_dp->psr_dpcd[1]); > > + return -ETIME; > > + } > > + > > + > > + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > > - 1) { > > + if (DISPLAY_VER(dev_priv) >= 20) { > > + /* setup entry frames can be set up to 3 > > frames */ > > + entry_setup_frames = 1; > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR setup entry frames set to > > %d\n", > > + entry_setup_frames); > > Don't refer "setting" here as this is just returning the value. Not setting it. Yes, just like previously I was thinking setting the register value but I will drop the "set" out here. Thanks for the review and comments! -Mika- > > BR, > > Jouni Högander > > > + } else { > > + drm_dbg_kms(&dev_priv->drm, > > + "PSR condition failed: PSR setup > > time (%d us) too long\n", > > + psr_setup_time); > > + return -ETIME; > > + } > > + } > > + > > + return entry_setup_frames; > > +} > > + > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > struct intel_crtc_state > > *crtc_state) > > { > > @@ -1213,7 +1273,7 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > const struct drm_display_mode *adjusted_mode = > > &crtc_state->hw.adjusted_mode; > > - int psr_setup_time; > > + u8 entry_setup_frames; > > > > /* > > * Current PSR panels don't work reliably with VRR enabled @@ > > -1242,19 +1302,13 @@ void intel_psr_compute_config(struct intel_dp > > *intel_dp, > > return; > > } > > > > - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); > > - if (psr_setup_time < 0) { > > - drm_dbg_kms(&dev_priv->drm, > > - "PSR condition failed: Invalid PSR setup > > time (0x%02x)\n", > > - intel_dp->psr_dpcd[1]); > > - return; > > - } > > + entry_setup_frames = > > intel_psr_set_entry_setup_frames(intel_dp, adjusted_mode); > > > > - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay > > - 1) { > > + if (entry_setup_frames >= 0) { > > + intel_dp->psr.entry_setup_frames = > > entry_setup_frames; > > + } else { > > drm_dbg_kms(&dev_priv->drm, > > - "PSR condition failed: PSR setup time (%d > > us) too long\n", > > - psr_setup_time); > > + "PSR condition failed: PSR setup timing > > not met\n"); > > return; > > } > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > index d39951383c92..efe4306b37e0 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > @@ -35,6 +35,8 @@ > > #define > > EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ > > ENTRY_TIME_MASK, 3) > > #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) > > #define > > EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP > > _TIME_MASK, (x)) > > +#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) > > +#define > > LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY > > _SETUP_FRAMES_MASK, (x)) > > #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) > > #define EDP_PSR_TP_MASK REG_BIT(11) > > #define > > EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, > > 0)
> -----Original Message----- > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > Sent: Monday, November 6, 2023 10:54 AM > To: Hogander, Jouni <jouni.hogander@intel.com> > Cc: Kahola, Mika <mika.kahola@intel.com>; intel-gfx@lists.freedesktop.org > Subject: Re: [PATCH v3] drm/i915/display: Support PSR entry VSC packet to be transmitted one frame earlier > > On Mon, Nov 06, 2023 at 08:40:52AM +0000, Hogander, Jouni wrote: > > On Fri, 2023-11-03 at 11:32 +0200, Mika Kahola wrote: > > > Display driver shall read DPCD 00071h[3:1] during configuration to > > > get PSR setup time. This register provides the setup time > > > requirement on the VSC SDP entry packet. If setup time cannot be met > > > with the current timings (e.g., PSR setup time + other blanking > > > requirements > blanking time), driver should enable sending VSC SDP > > > one frame earlier before sending the capture frame. > > > > > > BSpec: 69895 (PSR Entry Setup Frames 17:16) > > > > > > v2: Write frames before su entry to correct register (Ville, Jouni) > > > Move frames before su entry calculation to it's > > > own function (Ville, Jouni) > > > Rename PSR Entry Setup Frames register to indicate > > > Lunarlake specificity (Jouni) > > > v3: Modify setup entry frames calculation function to > > > return the actual frames (Ville) > > > Match comment with actual implementation (Jouni) > > > > > > Signed-off-by: Mika Kahola <mika.kahola@intel.com> > > > --- > > > .../drm/i915/display/intel_display_types.h | 1 + > > > drivers/gpu/drm/i915/display/intel_psr.c | 82 > > > +++++++++++++++-- > > > -- > > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 + > > > 3 files changed, 71 insertions(+), 14 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > > > b/drivers/gpu/drm/i915/display/intel_display_types.h > > > index 047fe3f8905a..92f06d67fd1e 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > > @@ -1708,6 +1708,7 @@ struct intel_psr { > > > u32 dc3co_exitline; > > > u32 dc3co_exit_delay; > > > struct delayed_work dc3co_work; > > > + u8 entry_setup_frames; > > > }; > > > > > > struct intel_dp { > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > > b/drivers/gpu/drm/i915/display/intel_psr.c > > > index ecd24a0b86cb..497e4c26f4a6 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > > @@ -592,6 +592,9 @@ static void intel_psr_enable_sink(struct > > > intel_dp > > > *intel_dp) > > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > > dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; > > > > > > + if (intel_dp->psr.entry_setup_frames > 0) > > > + dpcd_val |= DP_PSR_FRAME_CAPTURE; > > > + > > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > > > > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > > > DP_SET_POWER_D0); @@ -690,6 +693,9 @@ static void > > > hsw_activate_psr1(struct intel_dp > > > *intel_dp) > > > if (DISPLAY_VER(dev_priv) >= 8) > > > val |= EDP_PSR_CRC_ENABLE; > > > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > > + val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > > >psr.entry_setup_frames); > > > + > > > intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, > > > cpu_transcoder), > > > ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); > > > } > > > @@ -727,11 +733,27 @@ static int psr2_block_count(struct intel_dp > > > *intel_dp) > > > return psr2_block_count_lines(intel_dp) / 4; > > > } > > > > > > +static u8 get_frames_before_su_entry(struct intel_dp *intel_dp) { > > > + u8 frames_before_su_entry; > > > + > > > + frames_before_su_entry = max_t(u8, > > > + intel_dp- > > > >psr.sink_sync_latency + 1, > > > + 2); > > > + > > > + /* Entry setup frames must be at least 1 less than frames > > > before SU entry */ > > > + if (intel_dp->psr.entry_setup_frames >= > > > frames_before_su_entry) > > > + frames_before_su_entry = intel_dp- > > > >psr.entry_setup_frames + 1; > > > + > > > + return frames_before_su_entry; } > > > + > > > static void hsw_activate_psr2(struct intel_dp *intel_dp) > > > { > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > enum transcoder cpu_transcoder = intel_dp->psr.transcoder; > > > u32 val = EDP_PSR2_ENABLE; > > > + u32 psr_val = 0; > > > > > > val |= > > > EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); > > > > > > @@ -741,7 +763,8 @@ static void hsw_activate_psr2(struct intel_dp > > > *intel_dp) > > > if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= > > > 12) > > > val |= EDP_Y_COORDINATE_ENABLE; > > > > > > - val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp- > > > >psr.sink_sync_latency + 1, 2)); > > > + val |= > > > EDP_PSR2_FRAME_BEFORE_SU(get_frames_before_su_entry(intel_dp)); > > > + > > > val |= intel_psr2_get_tp_time(intel_dp); > > > > > > if (DISPLAY_VER(dev_priv) >= 12) { @@ -785,6 +808,9 @@ > > > static void hsw_activate_psr2(struct intel_dp > > > *intel_dp) > > > if (intel_dp->psr.req_psr2_sdp_prior_scanline) > > > val |= EDP_PSR2_SU_SDP_SCANLINE; > > > > > > + if (DISPLAY_VER(dev_priv) >= 20) > > > + psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp- > > > >psr.entry_setup_frames); > > > + > > > if (intel_dp->psr.psr2_sel_fetch_enabled) { > > > u32 tmp; > > > > > > @@ -798,7 +824,7 @@ static void hsw_activate_psr2(struct intel_dp > > > *intel_dp) > > > * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and > > > BSpec is > > > * recommending keep this bit unset while PSR2 is enabled. > > > */ > > > - intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > > cpu_transcoder), 0); > > > + intel_de_write(dev_priv, psr_ctl_reg(dev_priv, > > > cpu_transcoder), psr_val); > > > > > > intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); > > > } > > > @@ -1066,6 +1092,40 @@ static bool _compute_psr2_wake_times(struct > > > intel_dp *intel_dp, > > > return true; > > > } > > > > > > +static u8 intel_psr_set_entry_setup_frames(struct intel_dp > > > *intel_dp, > > > + const struct > > > drm_display_mode *adjusted_mode) > > > > I think "set" is not correct here. intel_psr_get_entry_setup_frames is > > more appropriate. > > I don't really like either. > > We don't generally say eg. get_sin(x) either, it's just sin(x). > > So IMO the correct name would be just intel_psr_entry_setup_frames(), or perhaps intel_psr_num_entry_setup_frames(). That > will make the code more like proper English when you read it outloud. I was thinking while writing this that we set the register with this value but since we don't actually set the register here the naming would be better phrased. > > > > > > +{ > > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > > You should use name i915 here. > > > > > + int psr_setup_time = drm_dp_psr_setup_time(intel_dp- > > > >psr_dpcd); > > > + u8 entry_setup_frames = 0; > > > + > > > + if (psr_setup_time < 0) { > > > + drm_dbg_kms(&dev_priv->drm, > > > + "PSR condition failed: Invalid PSR setup > > > time (0x%02x)\n", > > > + intel_dp->psr_dpcd[1]); > > > + return -ETIME; > > > + } > > > + > > > + > > > + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > +> > > > + adjusted_mode->crtc_vtotal - > > > +adjusted_mode->crtc_vdisplay > > > - 1) { > > > + if (DISPLAY_VER(dev_priv) >= 20) { > > > + /* setup entry frames can be set up to 3 > > > frames */ > > > + entry_setup_frames = 1; > > > + drm_dbg_kms(&dev_priv->drm, > > > + "PSR setup entry frames set to > > > %d\n", > > > + entry_setup_frames); > > > > Don't refer "setting" here as this is just returning the value. Not > > setting it. > > This kind of stuff should really all be moved to the crtc state proper, and then just dumped alongside everything else. Probably this is not the optimal place for this and could be moved out. Maybe update to this patch? Thanks! -Mika- > > > > > BR, > > > > Jouni Högander > > > > > + } else { > > > + drm_dbg_kms(&dev_priv->drm, > > > + "PSR condition failed: PSR setup > > > time (%d us) too long\n", > > > + psr_setup_time); > > > + return -ETIME; > > > + } > > > + } > > > + > > > + return entry_setup_frames; > > > +} > > > + > > > static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > > > struct intel_crtc_state > > > *crtc_state) > > > { > > > @@ -1213,7 +1273,7 @@ void intel_psr_compute_config(struct intel_dp > > > *intel_dp, > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > const struct drm_display_mode *adjusted_mode = > > > &crtc_state->hw.adjusted_mode; > > > - int psr_setup_time; > > > + u8 entry_setup_frames; > > > > > > /* > > > * Current PSR panels don't work reliably with VRR enabled > > > @@ -1242,19 +1302,13 @@ void intel_psr_compute_config(struct > > > intel_dp *intel_dp, > > > return; > > > } > > > > > > - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); > > > - if (psr_setup_time < 0) { > > > - drm_dbg_kms(&dev_priv->drm, > > > - "PSR condition failed: Invalid PSR setup > > > time (0x%02x)\n", > > > - intel_dp->psr_dpcd[1]); > > > - return; > > > - } > > > + entry_setup_frames = > > > intel_psr_set_entry_setup_frames(intel_dp, adjusted_mode); > > > > > > - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > > > > > > > - adjusted_mode->crtc_vtotal - > > > adjusted_mode->crtc_vdisplay > > > - 1) { > > > + if (entry_setup_frames >= 0) { > > > + intel_dp->psr.entry_setup_frames = > > > entry_setup_frames; > > > + } else { > > > drm_dbg_kms(&dev_priv->drm, > > > - "PSR condition failed: PSR setup time > > > (%d > > > us) too long\n", > > > - psr_setup_time); > > > + "PSR condition failed: PSR setup timing > > > not met\n"); > > > return; > > > } > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > > index d39951383c92..efe4306b37e0 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > > @@ -35,6 +35,8 @@ > > > #define > > > EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES > > > REG_FIELD_PREP(EDP_PSR_MIN_LINK_ ENTRY_TIME_MASK, 3) > > > #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) > > > #define > > > EDP_PSR_MAX_SLEEP_TIME(x) > > > REG_FIELD_PREP(EDP_PSR_MAX_SLEEP _TIME_MASK, (x)) > > > +#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) > > > +#define > > > LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) > > > REG_FIELD_PREP(LNL_EDP_PSR_ENTRY _SETUP_FRAMES_MASK, (x)) > > > #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) > > > #define EDP_PSR_TP_MASK REG_BIT(11) > > > #define > > > EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, > > > 0) > > > > -- > Ville Syrjälä > Intel
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 047fe3f8905a..92f06d67fd1e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1708,6 +1708,7 @@ struct intel_psr { u32 dc3co_exitline; u32 dc3co_exit_delay; struct delayed_work dc3co_work; + u8 entry_setup_frames; }; struct intel_dp { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ecd24a0b86cb..497e4c26f4a6 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -592,6 +592,9 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) if (intel_dp->psr.req_psr2_sdp_prior_scanline) dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; + if (intel_dp->psr.entry_setup_frames > 0) + dpcd_val |= DP_PSR_FRAME_CAPTURE; + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); @@ -690,6 +693,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) if (DISPLAY_VER(dev_priv) >= 8) val |= EDP_PSR_CRC_ENABLE; + if (DISPLAY_VER(dev_priv) >= 20) + val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); + intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); } @@ -727,11 +733,27 @@ static int psr2_block_count(struct intel_dp *intel_dp) return psr2_block_count_lines(intel_dp) / 4; } +static u8 get_frames_before_su_entry(struct intel_dp *intel_dp) +{ + u8 frames_before_su_entry; + + frames_before_su_entry = max_t(u8, + intel_dp->psr.sink_sync_latency + 1, + 2); + + /* Entry setup frames must be at least 1 less than frames before SU entry */ + if (intel_dp->psr.entry_setup_frames >= frames_before_su_entry) + frames_before_su_entry = intel_dp->psr.entry_setup_frames + 1; + + return frames_before_su_entry; +} + static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 val = EDP_PSR2_ENABLE; + u32 psr_val = 0; val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); @@ -741,7 +763,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) if (DISPLAY_VER(dev_priv) >= 10 && DISPLAY_VER(dev_priv) <= 12) val |= EDP_Y_COORDINATE_ENABLE; - val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); + val |= EDP_PSR2_FRAME_BEFORE_SU(get_frames_before_su_entry(intel_dp)); + val |= intel_psr2_get_tp_time(intel_dp); if (DISPLAY_VER(dev_priv) >= 12) { @@ -785,6 +808,9 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) if (intel_dp->psr.req_psr2_sdp_prior_scanline) val |= EDP_PSR2_SU_SDP_SCANLINE; + if (DISPLAY_VER(dev_priv) >= 20) + psr_val |= LNL_EDP_PSR_ENTRY_SETUP_FRAMES(intel_dp->psr.entry_setup_frames); + if (intel_dp->psr.psr2_sel_fetch_enabled) { u32 tmp; @@ -798,7 +824,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. */ - intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), 0); + intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), psr_val); intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); } @@ -1066,6 +1092,40 @@ static bool _compute_psr2_wake_times(struct intel_dp *intel_dp, return true; } +static u8 intel_psr_set_entry_setup_frames(struct intel_dp *intel_dp, + const struct drm_display_mode *adjusted_mode) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + int psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); + u8 entry_setup_frames = 0; + + if (psr_setup_time < 0) { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: Invalid PSR setup time (0x%02x)\n", + intel_dp->psr_dpcd[1]); + return -ETIME; + } + + + if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > + adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { + if (DISPLAY_VER(dev_priv) >= 20) { + /* setup entry frames can be set up to 3 frames */ + entry_setup_frames = 1; + drm_dbg_kms(&dev_priv->drm, + "PSR setup entry frames set to %d\n", + entry_setup_frames); + } else { + drm_dbg_kms(&dev_priv->drm, + "PSR condition failed: PSR setup time (%d us) too long\n", + psr_setup_time); + return -ETIME; + } + } + + return entry_setup_frames; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -1213,7 +1273,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - int psr_setup_time; + u8 entry_setup_frames; /* * Current PSR panels don't work reliably with VRR enabled @@ -1242,19 +1302,13 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); - if (psr_setup_time < 0) { - drm_dbg_kms(&dev_priv->drm, - "PSR condition failed: Invalid PSR setup time (0x%02x)\n", - intel_dp->psr_dpcd[1]); - return; - } + entry_setup_frames = intel_psr_set_entry_setup_frames(intel_dp, adjusted_mode); - if (intel_usecs_to_scanlines(adjusted_mode, psr_setup_time) > - adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { + if (entry_setup_frames >= 0) { + intel_dp->psr.entry_setup_frames = entry_setup_frames; + } else { drm_dbg_kms(&dev_priv->drm, - "PSR condition failed: PSR setup time (%d us) too long\n", - psr_setup_time); + "PSR condition failed: PSR setup timing not met\n"); return; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index d39951383c92..efe4306b37e0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -35,6 +35,8 @@ #define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3) #define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) #define EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x)) +#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) +#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK, (x)) #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) #define EDP_PSR_TP_MASK REG_BIT(11) #define EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, 0)
Display driver shall read DPCD 00071h[3:1] during configuration to get PSR setup time. This register provides the setup time requirement on the VSC SDP entry packet. If setup time cannot be met with the current timings (e.g., PSR setup time + other blanking requirements > blanking time), driver should enable sending VSC SDP one frame earlier before sending the capture frame. BSpec: 69895 (PSR Entry Setup Frames 17:16) v2: Write frames before su entry to correct register (Ville, Jouni) Move frames before su entry calculation to it's own function (Ville, Jouni) Rename PSR Entry Setup Frames register to indicate Lunarlake specificity (Jouni) v3: Modify setup entry frames calculation function to return the actual frames (Ville) Match comment with actual implementation (Jouni) Signed-off-by: Mika Kahola <mika.kahola@intel.com> --- .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 82 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 + 3 files changed, 71 insertions(+), 14 deletions(-)