| Message ID | 20231114141012.603960-1-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Fix fractional bpp handling in intel_link_bw_reduce_bpp() | expand |
On 11/14/2023 7:40 PM, Imre Deak wrote: > Convert crtc_state->pipe_bpp to U6.4 format as expected by the rest of > the function. > > Fixes: 59a266f068b4 ("drm/i915/display: Store compressed bpp in U6.4 format") > Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> > Cc: Suraj Kandpal <suraj.kandpal@intel.com> > Cc: Sui Jingfeng <suijingfeng@loongson.cn> > Signed-off-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/display/intel_link_bw.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c > index 02a0af2aa5bae..9c6d35a405a18 100644 > --- a/drivers/gpu/drm/i915/display/intel_link_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c > @@ -55,11 +55,11 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, > struct drm_i915_private *i915 = to_i915(state->base.dev); > enum pipe max_bpp_pipe = INVALID_PIPE; > struct intel_crtc *crtc; > - int max_bpp = 0; > + int max_bpp_x16 = 0; > > for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { > struct intel_crtc_state *crtc_state; > - int link_bpp; > + int link_bpp_x16; > > if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe)) > continue; > @@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, > return PTR_ERR(crtc_state); > > if (crtc_state->dsc.compression_enable) > - link_bpp = crtc_state->dsc.compressed_bpp_x16; > + link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; My apologies, I think, messed this up while rebasing :( Thanks for catching this. The change looks good to me. Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Regards, Ankit > else > /* > * TODO: for YUV420 the actual link bpp is only half > @@ -78,10 +78,10 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, > * is based on the pipe bpp value, set the actual link bpp > * limit here once the MST BW allocation is fixed. > */ > - link_bpp = crtc_state->pipe_bpp; > + link_bpp_x16 = to_bpp_x16(crtc_state->pipe_bpp); > > - if (link_bpp > max_bpp) { > - max_bpp = link_bpp; > + if (link_bpp_x16 > max_bpp_x16) { > + max_bpp_x16 = link_bpp_x16; > max_bpp_pipe = crtc->pipe; > } > } > @@ -89,7 +89,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, > if (max_bpp_pipe == INVALID_PIPE) > return -ENOSPC; > > - limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1; > + limits->max_bpp_x16[max_bpp_pipe] = max_bpp_x16 - 1; > > return intel_modeset_pipes_in_mask_early(state, reason, > BIT(max_bpp_pipe));
On Tue, Nov 14, 2023 at 09:50:37PM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915: Fix fractional bpp handling in intel_link_bw_reduce_bpp() > URL : https://patchwork.freedesktop.org/series/126403/ > State : success I didn't receive any CI shards results and I can't see the patch in the test queue either. However it fixes an obvious issue during module loading, so pushed it do -din, thanks for the review. > > == Summary == > > CI Bug Log - changes from CI_DRM_13875 -> Patchwork_126403v1 > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/index.html > > Participating hosts (39 -> 38) > ------------------------------ > > Additional (1): fi-pnv-d510 > Missing (2): fi-snb-2520m bat-dg1-5 > > Known issues > ------------ > > Here are the changes found in Patchwork_126403v1 that come from known issues: > > ### CI changes ### > > #### Issues hit #### > > * boot: > - bat-jsl-1: [PASS][1] -> [FAIL][2] ([i915#8293]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/bat-jsl-1/boot.html > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-jsl-1/boot.html > > > #### Possible fixes #### > > * boot: > - fi-hsw-4770: [FAIL][3] ([i915#8293]) -> [PASS][4] > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/fi-hsw-4770/boot.html > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-hsw-4770/boot.html > > > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_exec_suspend@basic-s3@smem: > - bat-rpls-1: [PASS][5] -> [ABORT][6] ([i915#7978]) > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-rpls-1/igt@gem_exec_suspend@basic-s3@smem.html > > * igt@i915_selftest@live@gt_heartbeat: > - fi-glk-j4005: [PASS][7] -> [DMESG-FAIL][8] ([i915#5334]) > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html > > * igt@i915_selftest@live@hangcheck: > - fi-hsw-4770: NOTRUN -> [INCOMPLETE][9] ([i915#9527]) > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html > > * igt@i915_suspend@basic-s3-without-i915: > - bat-atsm-1: NOTRUN -> [SKIP][10] ([i915#6645]) > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html > > * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: > - fi-hsw-4770: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#5190]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-hsw-4770/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html > > * igt@kms_busy@basic@modeset: > - bat-adlp-11: [PASS][12] -> [DMESG-FAIL][13] ([i915#6868]) > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/bat-adlp-11/igt@kms_busy@basic@modeset.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-adlp-11/igt@kms_busy@basic@modeset.html > > * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1: > - fi-hsw-4770: NOTRUN -> [SKIP][14] ([fdo#109271]) +12 other tests skip > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-vga-1.html > > * igt@kms_pipe_crc_basic@nonblocking-crc: > - bat-dg2-11: NOTRUN -> [SKIP][15] ([i915#1845] / [i915#9197]) > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc.html > > * igt@kms_pipe_crc_basic@suspend-read-crc: > - bat-atsm-1: NOTRUN -> [SKIP][16] ([i915#1836]) > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-atsm-1/igt@kms_pipe_crc_basic@suspend-read-crc.html > > * igt@kms_psr@primary_page_flip: > - fi-pnv-d510: NOTRUN -> [SKIP][17] ([fdo#109271]) +29 other tests skip > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-pnv-d510/igt@kms_psr@primary_page_flip.html > > * igt@kms_psr@sprite_plane_onoff: > - fi-hsw-4770: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#1072]) +3 other tests skip > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-hsw-4770/igt@kms_psr@sprite_plane_onoff.html > > > #### Possible fixes #### > > * igt@i915_selftest@live@gem_contexts: > - bat-atsm-1: [INCOMPLETE][19] ([i915#9174]) -> [PASS][20] > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/bat-atsm-1/igt@i915_selftest@live@gem_contexts.html > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-atsm-1/igt@i915_selftest@live@gem_contexts.html > > * igt@i915_selftest@live@gt_heartbeat: > - fi-apl-guc: [DMESG-FAIL][21] ([i915#5334]) -> [PASS][22] > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html > > * igt@kms_flip@basic-flip-vs-modeset@d-dp5: > - bat-adlp-11: [DMESG-FAIL][23] ([i915#6868]) -> [PASS][24] > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/bat-adlp-11/igt@kms_flip@basic-flip-vs-modeset@d-dp5.html > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-adlp-11/igt@kms_flip@basic-flip-vs-modeset@d-dp5.html > > * igt@kms_hdmi_inject@inject-audio: > - fi-kbl-guc: [FAIL][25] ([IGT#3]) -> [PASS][26] > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html > > * igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1: > - bat-rplp-1: [ABORT][27] ([i915#8668]) -> [PASS][28] > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13875/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html > > > {name}: This element is suppressed. This means it is ignored when computing > the status of the difference (SUCCESS, WARNING, or FAILURE). > > [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 > [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836 > [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 > [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 > [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 > [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645 > [i915#6868]: https://gitlab.freedesktop.org/drm/intel/issues/6868 > [i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978 > [i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293 > [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668 > [i915#9174]: https://gitlab.freedesktop.org/drm/intel/issues/9174 > [i915#9197]: https://gitlab.freedesktop.org/drm/intel/issues/9197 > [i915#9527]: https://gitlab.freedesktop.org/drm/intel/issues/9527 > > > Build changes > ------------- > > * Linux: CI_DRM_13875 -> Patchwork_126403v1 > > CI-20190529: 20190529 > CI_DRM_13875: 00536be456cfe5f687c0e782f8dfba7db666d89b @ git://anongit.freedesktop.org/gfx-ci/linux > IGT_7588: 328c5873b8f061267fdf86ed32cb5ecc611ba081 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git > Patchwork_126403v1: 00536be456cfe5f687c0e782f8dfba7db666d89b @ git://anongit.freedesktop.org/gfx-ci/linux > > > ### Linux commits > > bd5b812fe42c drm/i915: Fix fractional bpp handling in intel_link_bw_reduce_bpp() > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_126403v1/index.html
diff --git a/drivers/gpu/drm/i915/display/intel_link_bw.c b/drivers/gpu/drm/i915/display/intel_link_bw.c index 02a0af2aa5bae..9c6d35a405a18 100644 --- a/drivers/gpu/drm/i915/display/intel_link_bw.c +++ b/drivers/gpu/drm/i915/display/intel_link_bw.c @@ -55,11 +55,11 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, struct drm_i915_private *i915 = to_i915(state->base.dev); enum pipe max_bpp_pipe = INVALID_PIPE; struct intel_crtc *crtc; - int max_bpp = 0; + int max_bpp_x16 = 0; for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { struct intel_crtc_state *crtc_state; - int link_bpp; + int link_bpp_x16; if (limits->bpp_limit_reached_pipes & BIT(crtc->pipe)) continue; @@ -70,7 +70,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, return PTR_ERR(crtc_state); if (crtc_state->dsc.compression_enable) - link_bpp = crtc_state->dsc.compressed_bpp_x16; + link_bpp_x16 = crtc_state->dsc.compressed_bpp_x16; else /* * TODO: for YUV420 the actual link bpp is only half @@ -78,10 +78,10 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, * is based on the pipe bpp value, set the actual link bpp * limit here once the MST BW allocation is fixed. */ - link_bpp = crtc_state->pipe_bpp; + link_bpp_x16 = to_bpp_x16(crtc_state->pipe_bpp); - if (link_bpp > max_bpp) { - max_bpp = link_bpp; + if (link_bpp_x16 > max_bpp_x16) { + max_bpp_x16 = link_bpp_x16; max_bpp_pipe = crtc->pipe; } } @@ -89,7 +89,7 @@ int intel_link_bw_reduce_bpp(struct intel_atomic_state *state, if (max_bpp_pipe == INVALID_PIPE) return -ENOSPC; - limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1; + limits->max_bpp_x16[max_bpp_pipe] = max_bpp_x16 - 1; return intel_modeset_pipes_in_mask_early(state, reason, BIT(max_bpp_pipe));
Convert crtc_state->pipe_bpp to U6.4 format as expected by the rest of the function. Fixes: 59a266f068b4 ("drm/i915/display: Store compressed bpp in U6.4 format") Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Suraj Kandpal <suraj.kandpal@intel.com> Cc: Sui Jingfeng <suijingfeng@loongson.cn> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_link_bw.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)