| Message ID | 20231116131841.1588781-11-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Fix UHBR data, link M/N/TU and PBN values | expand |
On Thu, Nov 16, 2023 at 03:18:40PM +0200, Imre Deak wrote: > Simplify intel_dp_max_data_rate() using > drm_dp_bw_channel_coding_efficiency() to calculate the max data rate for > both DP1.4 and UHBR link rates. This trades a redundant multiply/divide > for readability. > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++------------- > 1 file changed, 12 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 209c27167e057..a93e8f6429d85 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -405,29 +405,27 @@ int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, > int > intel_dp_max_data_rate(int max_link_rate, int max_lanes) > { > - if (max_link_rate >= 1000000) { > - /* > - * UHBR rates always use 128b/132b channel encoding, and have > - * 97.71% data bandwidth efficiency. Consider max_link_rate the > - * link bit rate in units of 10000 bps. > - */ > - int max_link_rate_kbps = max_link_rate * 10; > - > - max_link_rate_kbps = DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000); > - max_link_rate = max_link_rate_kbps / 8; > - } > + int ch_coding_efficiency = > + drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate)); > + int max_link_rate_kbps = max_link_rate * 10; > > + /* > + * UHBR rates always use 128b/132b channel encoding, and have > + * 97.71% data bandwidth efficiency. Consider max_link_rate the > + * link bit rate in units of 10000 bps. > + */ > /* > * Lower than UHBR rates always use 8b/10b channel encoding, and have > * 80% data bandwidth efficiency for SST non-FEC. However, this turns > - * out to be a nop by coincidence, and can be skipped: > + * out to be a nop by coincidence: > * > * int max_link_rate_kbps = max_link_rate * 10; > * max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10); > * max_link_rate = max_link_rate_kbps / 8; > */ > - > - return max_link_rate * max_lanes; > + return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes, > + ch_coding_efficiency), > + 1000000 * 8); > } > > bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp) > -- > 2.39.2
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 209c27167e057..a93e8f6429d85 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -405,29 +405,27 @@ int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, int intel_dp_max_data_rate(int max_link_rate, int max_lanes) { - if (max_link_rate >= 1000000) { - /* - * UHBR rates always use 128b/132b channel encoding, and have - * 97.71% data bandwidth efficiency. Consider max_link_rate the - * link bit rate in units of 10000 bps. - */ - int max_link_rate_kbps = max_link_rate * 10; - - max_link_rate_kbps = DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps, 9671), 10000); - max_link_rate = max_link_rate_kbps / 8; - } + int ch_coding_efficiency = + drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate)); + int max_link_rate_kbps = max_link_rate * 10; + /* + * UHBR rates always use 128b/132b channel encoding, and have + * 97.71% data bandwidth efficiency. Consider max_link_rate the + * link bit rate in units of 10000 bps. + */ /* * Lower than UHBR rates always use 8b/10b channel encoding, and have * 80% data bandwidth efficiency for SST non-FEC. However, this turns - * out to be a nop by coincidence, and can be skipped: + * out to be a nop by coincidence: * * int max_link_rate_kbps = max_link_rate * 10; * max_link_rate_kbps = DIV_ROUND_DOWN_ULL(max_link_rate_kbps * 8, 10); * max_link_rate = max_link_rate_kbps / 8; */ - - return max_link_rate * max_lanes; + return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate_kbps * max_lanes, + ch_coding_efficiency), + 1000000 * 8); } bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
Simplify intel_dp_max_data_rate() using drm_dp_bw_channel_coding_efficiency() to calculate the max data rate for both DP1.4 and UHBR link rates. This trades a redundant multiply/divide for readability. Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 26 ++++++++++++------------- 1 file changed, 12 insertions(+), 14 deletions(-)